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Posted 5mo ago

CAD Tools Optimisation Engineer (Design Verification)

@ Apple
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Cambridge or London or Saint Albans
OnsiteFull Time
Responsibilities:optimise simulations, develop methodologies, deploy infrastructure
Requirements Summary:BS/MS/PhD in EE/CE/CS or software engineering; 5+ years RTL simulation experience; strong Linux/grid computing; Python or Perl scripting; team player under tight schedules.
Technical Tools Mentioned:Cadence tool chain, SystemVerilog, Verilog, VHDL, Linux, Python, Perl
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Job Description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Multifaceted, amazing people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! Do you love working on challenges that no one has solved yet? As a member of our dynamic group, you will have the unique and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. Apple’s CAD Hardware Tech team are responsible for automating processes in designing Apple’s chips which power everything from Apple Watch and Apple TV to iPhone and iPad. We have outstanding career opportunities for interns interested in applying their software knowledge towards developing Apple’s ground breaking methodologies. Working among the industry's best, we’re looking for those with talent and ambition to innovate the way we design computer chips, to provide the next technological leap and improve customer experiences.

Description

As an experienced CAD engineer, you will assist with delivering high quality infrastructure for automating chip design processes. Specifically as the chip designs are becoming larger than ever, there is a growing need to optimise the performance of simulation tools to maximise the efficiency and reduce resource requirements (both in compute time and space). The scope of work includes developing and deploying new methodologies with vendor and internal teams, supporting and debugging issues on large scale simulations.

Minimum Qualifications

  • BS, MS, or PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, Computer Science, Software Engineering or a related field
  • Minimum 5 years of experience working on RTL simulation tools
  • Strong foundation on Linux and grid computing systems
  • Knowledge of scripting languages such as Python or Perl
  • Strong interpersonal and analytical skills
  • Ability to work well within a team and be productive under tight schedules

Preferred Qualifications

  • Expert knowledge on Cadence tool chain
  • Familiarity with SystemVerilog / Verilog / VHDL
  • A curiosity about GPU / PMU / CPU / SOC architecture and micro-architecture