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HCLTech
Posted 19h ago

Developer - Silicon Platform Validation, Python

HCLTech
Austin, Texas, United States
$45k-$86k/yrOnsiteFull Time
Responsibilities
  • architecting memory layouts
  • reviewing layout designs
  • mentoring team members
Requirements
  • Expertise in memory layout design, SRAM, DRAM, Flash
  • Memory mapping
  • Address decoding
  • Timing closure
  • Schematic and layout editing
  • Physical verification
  • DRC/LVS, and post-layout simulation
Technical tools mentioned
Synopsys Memory CompilerCadence VirtuosoMentor GraphicsEDASRAMDRAMFlashDRC/LVS

Job description

Job Description
Developer - Silicon Platform Validation, Python
Austin, Texas

Job Summary

This role is responsible for architecting, designing, and delivering memory layout solutions within hardware and embedded systems projects. The individual serves as a subject matter expert, driving technical excellence and innovation by leveraging advanced memory mapping strategies and tools. They ensure project outcomes meet stringent quality standards and client requirements while fostering knowledge growth and technical leadership within the team.

Key Responsibilities

1. Architect and design advanced memory layouts using industry-standard tools such as Synopsys Memory Compiler and Cadence Virtuoso, ensuring optimal performance and reliability in silicon and embedded solutions.

2. Lead solution development for product and sustenance projects by applying expert knowledge in SRAM, DRAM, and Flash memory organization, guiding team members through implementation phases.

3. Provide subject matter expertise in memory mapping, address decoding, and timing closure, supporting complex problem-solving and technical escalations.

4. Evaluate project deliverables by reviewing schematic and layout designs for memory blocks using EDA tools, ensuring compliance with quality metrics and best practices.

5. Drive adoption of new memory technologies and methodologies, including non-volatile memory layouts and low-power design techniques, to maintain solution relevance and quality.

6. Mentor and train team members in memory layout concepts, EDA tool usage, and verification flows to strengthen team capability and mitigate delivery risks.

7. Collaborate with stakeholders to gather specifications and translate requirements into robust memory architecture solutions aligned with client domains and technology needs.

8. Recommend and implement value creation initiatives by benchmarking memory layout approaches, integrating industry best practices, and optimizing for performance and area efficiency.

Skill Requirements

1. Expert proficiency in memory layout design using Synopsys, Cadence, or Mentor Graphics EDA tools.

2. Excellent understanding of memory organization principles for SRAM, DRAM, Flash, and non-volatile memories.

3. Advanced skills in memory mapping, address decoding, and timing closure techniques.

4. Solid capability in schematic capture, layout editing, and physical verification for memory blocks.

5. Strong knowledge of low-power memory design and reliability optimization.

6. Experience with memory verification flows, DRC/LVS checks, and post-layout simulation.

Other Requirements

1. Certified Cadence Virtuoso Layout Designer (optional but valuable)

2. Synopsys Certified Memory Designer (optional but valuable)
Maximum Salary (US): 
86000
Minimum Salary (US): 
45000





Apply now



Information at a Glance

Why HCLTech?

At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first.

HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026 totaled $14.8 billion. 

 



Compensation and Benefits

A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year.

About HCLTech

Global technology providing digital, engineering, and cloud services.

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