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Posted 8mo ago

DFT Engineer - Advanced Process Platform(Scan / MBIST / BSD / Silicon Diagnosis)

@ MediaTek
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Hsinchu, Hsinchu, Taiwan
OnsiteFull Time
Responsibilities:defining architecture, inserting scan, debugging silicon
Requirements Summary:Deep DFT architecture and post-silicon test experience; hands-on with Synopsys/Tessent EDA, ATPG and MBIST; scripting (Tcl/Python/Perl); Verilog/SystemVerilog; 5+ years relevant experience.
Technical Tools Mentioned:Synopsys DFT Compiler, TetraMAX ATPG, Tessent, VCS, Xcelium, Tcl, Python, Perl, Verilog, SystemVerilog
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Job Description

Job Description

Join MediaTek's "DFT for Advanced Process Platform" team -- your work directly impacts Cloud ASIC reliability and yield at the most advanced process nodes (N4/N3/N2 and beyond).
- DFT Architecture & Insertion: Define and implement Scan (full-scan, compressor), MBIST, and BSD/JTAG strategies for advanced-node SoCs and chiplet/3D-IC designs; own end-to-end insertion flows with Synopsys / Siemens (Tessent) EDA tools.
- ATPG & Advanced Fault Models: Develop and optimize patterns for stuck-at, transition delay, cell-aware, and path-delay fault models; drive fault coverage closure and DRC-clean pattern delivery.
- Simulation & Verification: Validate DFT logic correctness through gate-level simulation (VCS/Xcelium); resolve DFT rule violations and coverage gaps pre-tapeout.
- Post-Silicon Bring-Up & Test: Lead DFT-related activities across CP / FT / HTOL / HVS -- test-mode validation, scan chain continuity, MBIST execution and repair verification. - Volume Diagnosis & Yield Ramp: Apply scan/
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Main Requirements and Qualifications

  1. [Technical] 1. Solid DFT architecture knowledge: Scan chain (full/compressor), MBIST (March algorithms, memory repair), Boundary Scan (IEEE 1149.x / 1687 IJTAG). 2. Hands-on experience with Synopsys DFT Compiler / TetraMAX ATPG and/or Siemens (Tessent) Scan / MemoryBIST / Diagnosis; familiarity with advanced fault models (cell-aware, transition delay, path-delay) is a strong plus. 3. Post-silicon test flow experience: CP / FT / HTOL / HVS bring-up, scan/MBIST debug, fail-log and diagnosis data interpretation for yield and RMA analysis. 4. Scripting (Tcl / Python / Perl) for DFT flow automation; Verilog/SystemVerilog for DFT RTL integration; HDL simulation (VCS/Xcelium) experience is a plus. [Others] 1. Proactive and self-driven -- takes full ownership and drives issues to closure, even across multiple teams. 2. Passionate about leading-edge process technology and Cloud ASIC trends -- genuinely curious about how N4/N3/N2 process changes affect testability. 3. Challenge-oriented mindset -- thrives in fast-paced, ambiguous environments; continuous learner who keeps up with evolving EDA capabilities and industry best practices. 4. Effective communicator -- able to collaborate in English and Mandarin with design, process, ATE, and yield engineering teams.