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Posted 3mo ago

Electrical Engineering/Physics/Computer Science Internship/Master Thesis Student (m/f/d) (Oberpfaffenhofen)

@ DLR
Oberpfaffenhofen, Bavaria, Germany
OnsiteInternship, Temporary
Responsibilities:setup FPGA, configure clock, setup SERDES
Requirements Summary:Internship/Master thesis student with basic VHDL, FPGA experience, Python skills, GitLab/CI, Docker, Linux, good English, problem solving.
Technical Tools Mentioned:VHDL, FPGA, Python, GitLab, CI/CD, Docker, Linux, openocd
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Job Description

The DLR Institute of Communications and Navigation is dedicated to mission-oriented research in selected areas of communications and navigation. Its work ranges from the theoretical foundations to the demonstration of new procedures and systems in a real environment and is embedded in DLR's Space, Aeronautics, Transport, Security and Digitalization programmes.

What to expect


Optical satellite links provide high and secure throughput both between satellites and between the satellites and the ground. In order to further increase throughput, coherent optical communication is one of the research areas of interest. To reduce hardware complexity of coherent optical receivers, the parts of the receiver may be shifted into the digital domain using intradyne receivers, opening up new possibilities for signal processing to compensate for channel effects such as Doppler shift and its rate, ADC/DAC sampling frequency offset as well as atmospheric turbulence.


This task aims to evaluate a new family of radiation-hardened FPGA SoCs for optical satellite communications. The works supports the goal of evaluating optical waveforms for robust communication within the space environment including Doppler shift and radiation effects, which is essential to enable technologies such as non-terrestrial 5G/6G networks.


The laboratory setup provided to the student consists of a radiation-hardened FPGA evaluation board, which is connected to a host Linux computer via JTAG and UART. The host computer is remotely accessible via SSH.


Your tasks



  • Setup of the FPGA design software suite inside Docker

  • Clock and UART configuration on FPGA

  • Setup of a high-speed SERDES interface in loopback configuration

  • External connection of SERDES interface and measurement with oscilloscope

  • Integration into GitLab CI


Your profile 



  • Basic programming skills in VHDL

  • Experience with FPGA hardware

  • Good programming skills in Python

  • Experience with git, tcl, GitLab, CI/CD, Docker, Linux, openocd optional

  • Fundamentals on statistics, linear algebra, signal theory, optical transmitters/receivers optional

  • Good English knowledge

  • Good problem-solving skills

 We look forward to getting to know you!

 

If you have any questions about this position (Vacancy-ID 3862) please contact:

 

Dr. Juraj Poliak 
Tel.: +49 8153 28 1470