Posted 2w ago

IC Layout Engineer

Silicon Technologies

silicontechnologiesinc.com View all open roles

Midvale, Utah, United States

OnsiteFull Time

Responsibilities

creating cells
designing layouts
verifying compliance

Requirements

Create DRC/LVS/DFM-clean library cells for advanced process nodes and radiation-hardened layouts
Experience with Cadence Virtuoso required

Technical tools mentioned

DRCLVSDFMCadence Virtuoso

Job description

Create DRC/LVS/DFM-clean library cells for the ADONIS Correct-by-Architecture methodology. Work on advanced process nodes and radiation-hardened layouts. Experience with Cadence Virtuoso required.

About Silicon Technologies

Designs and licenses analog and mixed-signal semiconductor IP.

Year founded

2009

Employees

Industries

Semiconductors Electronic Design Automation

Activities

Analog circuit design Mixed-signal IC design Semiconductor IP licensing Radiation-hardened design Electronic design automation

Organization type

Private

Headquarters