29 analog engineer jobs at 11 companies in Eloy, AZ
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Staff Analog Engineer
Chandler, Arizona, United States
OnsiteFull Time
5+ YOEBachelor's or master's degree in electrical or computer engineering and 5–10+ years of analog design experience; strong communication and teamwork skills required.
CMOS, DFT
2mo
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Power/Analog Engineer
Tempe, Arizona, United States
$95k-$150k/yr OnsiteFull Time
3+ YOE3+ years analog and power converter design experience, familiarity with oscilloscopes/current probes/FRA/multimeters, Bachelor's in Electrical Engineering, U.S. citizenship required, up to 10% domestic travel, ability to obtain Secret clearance.
PSPICE, LTSPICE, HSPICE, Mentor Graphics XxDesigner, ORCAD Capture, Mentor Graphics Expedition, Zuken, oscilloscopes, current probes, frequency response analyzer, multimeters
1mo
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Analog Design Engineer
Scottsdale or Chandler or Phoenix
$134k-$168k/yr OnsiteFull Time
10+ YOEBachelor's in Electronic Engineering, 10+ years analog IC design experience, proficiency with Cadence Virtuoso and Mentor Graphics, EM/ESD awareness, bench testing skills, scripting (SKILL/Perl/Python/TCL) a plus, strong communication.
Cadence Virtuoso, Mentor Graphics, SKILL, Perl, Python, TCL
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Analog Design Engineer
Phoenix or Hillsboro or Chandler
$122k-$173k/yr OnsiteFull Time
2+ YOEBachelor's degree plus 3+ years or master's degree plus 2+ years in circuit design; knowledge of analog IC design, circuit simulation, signal and power integrity, layout, and Cadence tools.
SPICE, Cadence, Synopsys, LTspice, Cadence analog IC design tools, Python, MATLAB
3d
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Principal Analog Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEMSEE required; 10+ years developing mixed-signal ICs, preferably 5+ years as an architect or technical leader. Requires analog transistor-level design, DC-DC architecture, Cadence tools, and English communication.
Cadence Virtuoso, Cadence Spectre, Cadence AMS
2mo
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Senior Technical Staff Engineer – IC Analog Design
Chandler, Arizona, United States
OnsiteFull Time
12+ YOESenior IC analog design engineer with 12+ years, DAC/ADC expertise, CMOS design, lab testing, Cadence tools, scripting.
Cadence Virtuoso, Cadence Spectre, MATLAB, Python, Tcl
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Senior DDR Analog Characterization Engineer
Chandler, Arizona, United States
$198k-$268k/yr HybridFull Time
Bachelor's or master's degree in electrical or computer engineering, 3.0+ GPA, DDR/LPDDR validation experience, signal integrity and timing expertise, laboratory equipment experience, and strong communication skills.
DDR5, LPDDR6, Python
2mo
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Analog Mixed Signal Modeling Engineer (UL - 02)
Austin or Chandler or Greensboro
HybridFull Time
Master's in EE/Computer Eng required. Experience in mixed-signal product development, analog IC design, SystemVerilog RNM, AMS simulators, verification methodologies, and strong analytical and communication skills.
SystemVerilog Real Number Modeling (SV-RNM), Verilog AMS, AMS simulators, System Verilog Assertions, PSL Assertions, Perforce, GIT, UVM, Simulink, Simscape, Python
4d
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I/O Design Engineer
Chandler, Arizona, United States
$110k-$176k/yr OnsiteFull Time
6+ YOERequires an MS or PhD in Electrical Engineering, 6+ years of I/O or analog circuit design experience, and proficiency with Cadence Virtuoso, SPICE/Spectre, CMOS processes, and I/O protocols.
Cadence Virtuoso, SPICE, Spectre, Verilog, Synopsys Liberty, IBIS, GPIO, I2C, I3C, eMMC, RGMII, SPMI
2w
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Electrical Engineer / Counter-UAS
Gilbert, Arizona, United States
OnsiteFull Time
5+ YOEBachelor's in EE,5+ years electrical design and system integration,experience with power distribution,analog/digital circuitry,PCB tools,EMI/EMC,communication protocols,and ability to obtain security clearance.
Altium, OrCAD, KiCad, UART, SPI, I2C, Ethernet, CAN
1mo
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Principal Design Engineer
Chandler or Phoenix or Raleigh or Durham
OnsiteFull Time
10+ YOEBSEE/MSEE with 10+ years experience in precision analog/mixed-signal design; transistor-level design ownership, system-to-block requirements translation, DFT/simulation, EMR of product development; familiarity with Cadence AMS, JAMA, GIT; System Verilog desired.
Cadence Analog and Mixed Signal Tool Suite, JAMA, GIT, system Verilog
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