6 analog engineer jobs at 5 companies in Wheatland, CA
3d
Save
Mark Applied
Hide
Member of Technical Staff, Design
San Jose or Roseville or Hudson
$169k-$288k/yr OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
18+ YOEBS in Electrical Engineering plus 18 years of experience or MS plus 14 years; extensive analog IC, power management, control-loop, semiconductor, and IC release expertise required.
Simplis, MATLAB, Cadence Spectre, CMOS, LDMOS
2w
Save
Mark Applied
Hide
Electronics Engineer II
Rancho Cordova, California, United States
$80k-$85k/yr OnsiteFull Time
5+ YOEBachelor's degree in electronic engineering with 5+ years of engineering experience, or associate degree with 9+ years. Requires PCB design, electronic testing, troubleshooting, analog/digital/embedded design, and communication skills.
PCAD, Altium, AutoCAD, VHDL, PCB, oscilloscope, DVM, Logic analyzers
3mo
Save
Mark Applied
Hide
Senior Electrical Engineer
Irving or Bronx or Sacramento or Dallas
$125k-$135k/yr OnsiteFull Time
10+ YOE10+ years electrical engineering; analog/digital circuit design; up to 600VAC; PCB layout; Ethernet/CAN/RS232; elevator domain knowledge.
Altium, Embedded C, FPGA, CAN, Ethernet, RS232/422
1w
Save
Mark Applied
Hide
Staff Layout Design Engineer
Raleigh or Sacramento or Tallahassee or Denver or Austin
$144k-$188k/yr OnsiteFull Time
10+ YOEAssociate degree in electronic or IC layout CAD or related field and 10+ years of IC layout experience. Requires analog layout, floorplanning, Cadence and Mentor tools, LVS troubleshooting, and teamwork skills.
Cadence Virtuoso XL, Mentor Calibre, Cadence, Mentor, CMOS, SOI, PDK, LVS
3w
Save
Mark Applied
Hide
Principal SerDes Architect
Santa Clara or Hillsboro or Folsom or Phoenix
$221k-$312k/yr HybridFull Time
10+ YOEBachelor's in EE/CE with 12+ years (or Master's with 10+ years) in analog circuit design; deep SerDes and I/O PHY expertise; analog modeling, simulation, optimization; UCIe/PCIe familiarity; technical leadership and mentoring.
UCIe, PCIe, SerDes
2mo
Save
Mark Applied
Hide
Staff/Principal Layout Designer, AI-Optimized Memory
Richardson or Folsom
$62-$122/hr OnsiteFull Time
Bachelor's or Master's in CS/CE/EE (or equivalent), extensive DRAM layout experience, proficiency with Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS, and strong analog/mixed-signal layout fundamentals.
Cadence VLE/VXL, Mentor Graphics Calibre DRC/LVS