8 cmo jobs at 5 companies in Eloy, AZ
2mo
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Senior Technical Staff Engineer – IC Analog Design
Chandler, Arizona, United States
OnsiteFull Time
12+ YOESenior IC analog design engineer with 12+ years, DAC/ADC expertise, CMOS design, lab testing, Cadence tools, scripting.
Cadence Virtuoso, Cadence Spectre, MATLAB, Python, Tcl
2mo
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Senior Staff Analog Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
8+ YOE8+ years analog IC design experience; technical leadership of CMOS power management circuits, simulation/layout oversight, mentoring, customer-facing communication, and occasional international travel.
2d
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I/O Design Engineer
Chandler, Arizona, United States
$110k-$176k/yr OnsiteFull Time
6+ YOERequires an MS or PhD in Electrical Engineering, 6+ years of I/O or analog circuit design experience, and proficiency with Cadence Virtuoso, SPICE/Spectre, CMOS processes, and I/O protocols.
Cadence Virtuoso, SPICE, Spectre, Verilog, Synopsys Liberty, IBIS, GPIO, I2C, I3C, eMMC, RGMII, SPMI
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Principal Analog Design Engineer
Chandler, Arizona, United States
HybridFull Time
12+ YOE12+ years experience in power management ICs, degree in electronics engineering, technical project lead experience, CMOS power management expertise, strong communication and mentoring skills, occasional international travel.
3w
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Senior Analog Design Engineer
Chandler, Arizona, United States
HybridFull Time
5+ YOE5+ years analog/mixed-signal IC design experience; hands-on CMOS analog circuit design; Cadence/EDA tool proficiency; bachelor’s in electrical-related field; strong analytical, communication, and mentorship skills.
EDA, Cadence
1mo
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Experienced Program Manager - OTA Project (Other Transaction Agreement)
Tucson, Arizona, United States
OnsiteFull Time
Manage OTA program compliance and reporting, interface with CMO/government, track finances and schedules, ensure ITAR/EAR/CUI compliance, bachelor’s degree or equivalent, strong PM and communication skills, MS Office/MS Project proficiency.
MS Office, MS Project
1mo
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Staff Power IC Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
7+ YOEMSEE (7+ years) or PhD (5+ years) in power IC design, strong transistor-level design skills, tape-out/silicon validation experience, BCD/HV-CMOS knowledge, Cadence Virtuoso/Spectre/APS proficiency, control-loop and stability expertise.
Cadence Virtuoso, Spectre, APS
2mo
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Principal Power IC Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
8+ YOEMSEE (10+ yrs) or PhD (8+ yrs) power IC design experience; transistor-level design of power management circuits; experience with BCD/HV-CMOS, control-loop design; proficiency with Cadence Virtuoso and Spectre/APS; leadership from concept to silicon.
Cadence Virtuoso, Spectre/APS