18 cmo jobs at 13 companies in Hutto, TX
1mo
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Senior Editor, The CMO Club
United States or San Diego or Austin or Chicago or Denver or Jersey City or Tampa or Vancouver
$100k-$130k/yr RemoteFull Time
Senior editorial leader with experience creating B2B/practitioner-led content, growing newsletter and audience engagement, multimedia formats, strong interviewing and synthesis skills, SEO and analytics (Marfeel, GA, HubSpot).
Marfeel, GA, HubSpot
2mo
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CPU Memory Design Engineer
Austin, Texas, United States
$164k-$269k/yr HybridFull Time
6+ YOEBachelor's +6+ yrs or Master's +5+ yrs or PhD +2+ yrs; CMOS design; VLSI; memory design; power/performance/area trade-offs.
CMOS, VLSI, EDA tools, signal integrity
2d
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Sr Director, Business Development - Industrial
United States or Austin
$189k-$259k/yr RemoteFull Time
9+ YOEBachelor's degree in engineering, sciences, or business; typically 9 years of related experience; EMS, CMO, or engineering business experience; strategic selling and financial analysis skills.
2w
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Staff Mixed-Signal Design Engineer
Austin or Wilmington or Toronto or San Diego or Durham
$131k-$190k/yr HybridFull Time
7+ YOEM.S. in Electrical Engineering,7+ years CMOS design experience,strong analog circuit knowledge,Cadence and SPICE experience,MATLAB familiarity,good communication and teamwork skills.
Cadence, SPICE, MATLAB
1mo
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Austin Hiring Event - Senior Physical Design Engineer
Austin, Texas, United States
$95k-$141k/yr OnsiteFull Time
Bachelor's in CS/EE or equivalent experience; experience in block-level PnR for advanced CMOS nodes; proficiency with industry EDA tools; strong technical and critical thinking skills.
Cadence Genus, Innovus, Synopsys Design Compier, IC Compiler, Fusion Compiler, Tempus, PrimeTime, Voltus, PrimeRail, Calibre, LEC, Formality
3mo
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Physical Design Engineer II (Silicon Engineering)
Bastrop or Irvine or Sunnyvale
OnsiteFull Time
3+ YOEBachelor’s in EE/CE/CS; 3+ years RTL2GDSII physical design; expert in EDA tools; knowledge of FinFET/CMOS; scripting skills; ITAR compliance; available for extended hours.
EDA tools, Python, Perl, TCL, Bash
6d
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Yield and PCI (Process Control Innovation) Engineer
Taylor, Texas, United States
$76k-$145k/yr OnsiteFull Time
Requires an engineering or science degree, semiconductor device physics and CMOS fabrication knowledge, SPC expertise, analytical problem-solving, technical communication, and ability to work in a 24/7 cleanroom environment.
Statistical Process Control (SPC), CMOS, Lithography, Etch, Thin Films, Chemical Mechanical Planarization (CMP), Diffusion, Implant
1mo
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Principal Mixed-Signal Design Engineer
Wilmington or Toronto or Austin or San Diego or Durham
$157k-$227k/yr HybridFull Time
14+ YOEM.S. in Electrical Engineering, 14+ years CMOS design experience, high-speed data converter expertise, Cadence and SPICE experience, MATLAB familiarity, strong communication and team collaboration skills.
Cadence, SPICE, MATLAB
1mo
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Semiconductor Device Engineer
Austin, Texas, United States
$110k-$180k/yr OnsiteFull Time
Degree in EE/Applied Physics or related, strong CMOS device physics knowledge, probe station and lab experience, parameter extraction/BSIM familiarity, test automation and semiconductor fabrication experience.
BSIM, PDKs, probe station
1mo
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Sales Development Representative (Remote)
Austin or United States
RemotePart Time, Full Time
2+ YOE2+ years B2B marketing lead-generation experience, strong B2B writing and messaging skills, CRM proficiency, ability to analyze messaging performance and engage CMOs/VPs to book initial meetings.
Customer Relationship Management (CRM), LinkedIn, TikTok
3w
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Staff Mixed-Signal Design Engineer
Wilmington or Toronto or Austin or San Diego or Durham
$131k-$190k/yr HybridFull Time
5+ YOEM.S. or higher in Electrical Engineering,5+ years CMOS design experience,knowledge of wideband amplifiers,comparators,switched-capacitor circuits,LDOs;Cadence and SPICE experience;MATLAB and signal-processing knowledge.
Cadence, SPICE, MATLAB
1d
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SRAM/ROM Circuit Design Engineer
Austin, Texas, United States
HybridFull Time
8+ YOEBachelor's degree in electrical or computer engineering, 8+ years of SRAM memory circuit design experience, advanced CMOS experience at 5nm and beyond, Cadence Virtuoso, EDA tools, and Perl, Tcl, or Python scripting.
Cadence Virtuoso, EDA, Perl, Tcl, Python, LLM, GenAI
1mo
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Silicon Technology Manager
Austin, Texas, United States
HybridFull Time
10+ YOE3+ MgmtMaster's or Ph.D. in a relevant technical field, 10+ years in semiconductor technology or process integration, 3+ years technical leadership, CMOS/process integration expertise, foundry collaboration, strong analytical and communication skills.
1mo
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Analog Layout Design Engineer
Hillsboro or Austin
$122k-$173k/yr HybridFull Time
3+ YOEBachelor's in EE/CE (or equivalent) with 3+ years (or MS with 2+ years). Experience in analog layout, Cadence Virtuoso, Calibre/ICV DRC, CMOS technologies, floorplanning, verification, and debugging layout-related issues.
Cadence Virtuoso Layout Suite, Calibre, ICV DRC, LVS, DRC, xtract, SPEF
1mo
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Analog Engineer
Hillsboro or Santa Clara or Austin or Phoenix
$164k-$269k/yr HybridFull Time
4+ YOEBachelor's/Master's/PhD in EE/CE or related field with 4+–8+ years analog/mixed-signal design experience; expertise in analog circuit design, CMOS, tape-out, and verification; strong collaboration and problem-solving skills.
2w
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Product Engineer II (EMIR / PDN Analysis & Power Integrity)
Austin, Texas, United States
$102k-$189k/yr OnsiteFull Time
3+ YOEBachelor�s or Master�s in Electrical/VLSI Engineering, 3+ years related experience (or Masters), skills in digital/VLSI/CMOS design, power IR drop analysis, placement-and-routing flows, IR/EM debugging, Python or TCL, strong communication.
Python, TCL
2mo
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in EE, 10+ years digital CMOS IC design experience, Verilog/System Verilog expertise, low-power (UPF/CPF) and clocking/CDC/RDC knowledge, AXI/AHB/APB experience, scripting (Python/Perl/Tcl), and leadership of small design teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, C, Python, Perl, Tcl, Perforce, Git, Methodics
2mo
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in Electrical Engineering, 10+ years digital CMOS IC design experience, expertise in Verilog/System Verilog, UPF/CPF, AXI/AHB/APB, RTL design, synthesis, timing, power analysis, simulation, scripting (Python/Perl/Tcl), and leading small teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, RISC-V, C, Python, Perl, Tcl, Perforce, Git, Methodics