PromotedHiringCafe
Founding Head of Marketing
Cupertino, CA, US
$130k-$300k/yr On-SiteFull Time
Take HiringCafe from 1M to 10M+ MAUs. Founding marketing leader who lives on social, ships virally, and works hand-in-hand with engineering. 50+ hrs/week in our Cupertino office.
2w
Save
Mark Applied
Hide
Executive Coordinator, CMO Office
Austin, Texas, United States
HybridFull Time
Experience in high-touch support (talent/production/celebrity assistant or similar), exceptional written and verbal communication, proactive judgment, based in Austin, TX with flexibility to travel, curiosity about AI.
Claude, OpenAI
1mo
Save
Mark Applied
Hide
Senior Editor, The CMO Club
United States or San Diego or Austin or Chicago or Denver or Jersey City or Tampa or Vancouver
$100k-$130k/yr RemoteFull Time
Senior editorial leader with experience creating B2B/practitioner-led content, growing newsletter and audience engagement, multimedia formats, strong interviewing and synthesis skills, SEO and analytics (Marfeel, GA, HubSpot).
Marfeel, GA, HubSpot
3mo
Save
Mark Applied
Hide
Customer Program Manager— Feature‑Rich CMOS Product Line
Austin, Texas, United States
$118k-$210k/yr OnsiteFull Time
5+ YOE5+ years in semiconductors in program management or related roles; strong CMOS technical capability, program management discipline, executive communication, and customer advocacy skills.
3mo
Save
Mark Applied
Hide
GPU Physical Design Engineer
Austin, Texas, United States
OnsiteFull Time
Bachelor's in engineering or CS; PD/RTL/DFT/clocking knowledge; scripting in TCL/Python/Perl/shell; experience with CMOS/VLSI concepts.
Python, TCL, Perl, Shell scripting
1mo
Save
Mark Applied
Hide
CPU Memory Design Engineer
Austin, Texas, United States
$164k-$269k/yr HybridFull Time
6+ YOEBachelor's +6+ yrs or Master's +5+ yrs or PhD +2+ yrs; CMOS design; VLSI; memory design; power/performance/area trade-offs.
CMOS, VLSI, EDA tools, signal integrity
1mo
Save
Mark Applied
Hide
Senior Principal Mixed-Signal Design Engineer
Wilmington or Toronto or Austin or San Diego or Durham
$184k-$266k/yr HybridFull Time
20+ YOESenior-level mixed-signal design with 20+ years CMOS experience; MS in Electrical Engineering; expertise in high-speed data converters; CAD tools; MATLAB.
Cadence, SPICE, MATLAB
2w
Save
Mark Applied
Hide
Austin Hiring Event - Senior Physical Design Engineer
Austin, Texas, United States
$95k-$141k/yr OnsiteFull Time
Bachelor's in CS/EE or equivalent experience; experience in block-level PnR for advanced CMOS nodes; proficiency with industry EDA tools; strong technical and critical thinking skills.
Cadence Genus, Innovus, Synopsys Design Compier, IC Compiler, Fusion Compiler, Tempus, PrimeTime, Voltus, PrimeRail, Calibre, LEC, Formality
3mo
Save
Mark Applied
Hide
Digital Design Engineer
Austin or Greensboro or Chandler
HybridFull Time
2+ YOEDegree in Electrical or Computer Engineering; 2+ years digital IC design; Verilog RTL; digital design flow; state machines; CMOS VLSI knowledge; strong problem solving.
Verilog, UVM, MATLAB, Simulink
2mo
Save
Mark Applied
Hide
Physical Design Engineer II (Silicon Engineering)
Bastrop or Irvine or Sunnyvale
OnsiteFull Time
3+ YOEBachelor’s in EE/CE/CS; 3+ years RTL2GDSII physical design; expert in EDA tools; knowledge of FinFET/CMOS; scripting skills; ITAR compliance; available for extended hours.
EDA tools, Python, Perl, TCL, Bash
1mo
Save
Mark Applied
Hide
Sales Development Representative (Remote)
Austin or United States
RemotePart Time, Full Time
2+ YOE2+ years B2B marketing lead-generation experience, strong B2B writing and messaging skills, CRM proficiency, ability to analyze messaging performance and engage CMOs/VPs to book initial meetings.
Customer Relationship Management (CRM), LinkedIn, TikTok
1mo
Save
Mark Applied
Hide
Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in EE, 10+ years digital CMOS IC design experience, Verilog/System Verilog expertise, low-power (UPF/CPF) and clocking/CDC/RDC knowledge, AXI/AHB/APB experience, scripting (Python/Perl/Tcl), and leadership of small design teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, C, Python, Perl, Tcl, Perforce, Git, Methodics
1mo
Save
Mark Applied
Hide
Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in Electrical Engineering, 10+ years digital CMOS IC design experience, expertise in Verilog/System Verilog, UPF/CPF, AXI/AHB/APB, RTL design, synthesis, timing, power analysis, simulation, scripting (Python/Perl/Tcl), and leading small teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, RISC-V, C, Python, Perl, Tcl, Perforce, Git, Methodics