2mo
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DMTS Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years ASIC/digital design experience with prior tape-out; BS/MS/PhD in EE/CE or related; expert SystemVerilog; synthesis (Design Compiler/Genus), static timing analysis (PrimeTime/Tempus), RTL simulation (VCS/Xcelium), CDC tools; chip architecture and IP integration experience.
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold
2mo
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Senior SOC Physical Design Engineer, HBM
Richardson, Texas, United States
OnsiteFull Time
3+ YOEHands-on SoC physical implementation experience using EDA tools (Innovus, Fusion Compiler, Calibre, ICV, PrimeTime/Tempus); knowledge of SDC, UPF/CPF, static timing analysis, signoff flows; 3+ years physical design or SoC implementation experience; Tcl/Python scripting preferred.
Innovus, Fusion Compiler, IC Validator (ICV), Calibre, PrimeTime, Tempus, Synopsys Design Constraints (SDC), Unified Power Format (UPF), Common Power Format (CPF), Ansys, Tcl, Python
2d
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Quality Engineer - Sprout
Dallas, Texas, United States
OnsiteFull Time
2+ YOEMaintain quality programs, develop inspection/test methods, initiate corrective actions, compile quality data; typically requires a bachelor\u0002s degree and ~2 years experience.
oscilloscope, cable and harness testing, component testing, logic analyzer, microscope, schematics, PCB operations, measuring tools
3mo
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Principal Engineer Digital Design
Irvine or California or Dallas or Texas
$164k-$241k/yr HybridFull Time
12+ YOEBachelor's degree in EE/Computer Engineering, 12+ years RTL design experience (Verilog/System Verilog), DSP algorithm implementation, fixed-point math, MATLAB/C/C++, FPGA/ASIC experience, and familiarity with EDA tools (Synopsys Design Compiler, Cadence).
Verilog, System Verilog, HDL, MATLAB, Simulink, C, C++, Synopsys Design Compiler, Cadence