1mo
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Engineer, ASIC Physical Design
Minneapolis, Minnesota, United States
$143k-$176k/yr FieldFull Time
Experience with chip floor-planning, placement and routing, power/clock routing, static timing analysis (Tempus or PrimeTime), place-and-route (Innovus, ICC2, Fusion Compiler), physical verification (Calibre, IC Validator, Hercules), and scripting with Tcl/Cshell. Master's in EE/CE or related accepted.
Tempus, PrimeTime, Innovus, ICC2, Fusion Compiler, Calibre, IC Validator, Hercules, Tcl, Cshell
2mo
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DMTS Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years ASIC/digital design experience with prior tape-out; BS/MS/PhD in EE/CE or related; expert SystemVerilog; synthesis (Design Compiler/Genus), static timing analysis (PrimeTime/Tempus), RTL simulation (VCS/Xcelium), CDC tools; chip architecture and IP integration experience.
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold
4d
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Senior Software Engineer
Minneapolis, Minnesota, United States
$90k-$120k/yr HybridFull Time
2+ YOEBachelor's or equivalent experience, 2+ years software development, competency in compiled (Rust,C/C++) and interpreted (Python,JavaScript/TypeScript) languages, experience with SQL, Kubernetes, and software tooling.
Rust, C/C++, Python, JavaScript/TypeScript, JSON, XML, SQL, Kubernetes, DirectX, OpenGL, VS, VS Code, Git, Docker, Jenkins