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Lead - SoC Architect
San Jose, California, United States
$235k-$402k/yr OnsiteFull Time
MS or PhD in Electrical/Computer Engineering (required). Expert in heterogeneous SoC architecture (CPUs, GPUs, AI accelerators), memory and interconnect design, system-level modeling, and technical leadership across cross-functional teams.
2mo
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DFx Methodology Architect
San Jose, California, United States
OnsiteFull Time
Bachelor or Master in computer engineering or Electrical Engineering; experience with RTL design, DFx, IP development, and scripting languages.
Perl, TCL, Python, Verilog
1mo
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DFx Methodology Architect
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expert in DFx architecture, RTL implementation (Verilog/SystemVerilog), timing and DFT; experience with Siemens Tessent flows, ATPG, IJTAG, SSN; scripting (Perl, Python, TCL); silicon debug; degree in computer/electrical engineering.
Verilog, SystemVerilog, Siemens Tessent, Tessent Shell, Tessent Scan, Tessent ATPG, Tessent MemoryBist, IJTAG, SSN, Perl, Python, TCL
1mo
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AI Systems Architect – GPU Software/Hardware Co-Design
San Jose, California, United States
$151k-$258k/yr HybridFull Time
Experienced engineer in GPU software/hardware co-design, AI workload optimization, kernel optimization (HIP/CUDA/PTX/SASS), open-source contributions, and hardware bring-up. Degree in computer engineering, computer science, electrical engineering, or related field.
SGLang, vLLM, DSLs, HIP, CUDA, PTX, SASS, GitHub
1w
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SoC Architect
San Jose, California, United States
HybridFull Time
Expertise architecting SoC and I/O subsystems (PCIe/CXL/UAL), BS/MS/PhD in electrical or computer engineering or related field, strong communication, and domain experience in embedded/data-center/automotive/aerospace.
PCIe, CXL, UAL, Confidential Compute, FPGA, AXI, x86, RISC-V, ARM
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High Speed IO Analog Mixed Signal Architect/ Design Engineer
San Jose, California, United States
$216k-$324k/yr HybridFull Time
MS/PhD in Electrical or Computer Engineering; experience designing high-speed IO, memory PHYs and mixed-signal blocks; leadership and cross-functional collaboration; proficiency with AMS flows and circuit verification/characterization.
Cadence, Virtuoso, Spectre, HSPICE