9 dft engineer jobs at 7 companies in Portland, OR
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Product Engineer - Tessent Design for Test (DFT)
Wilsonville, Oregon, United States
$35-$64/hr HybridFull Time
1+ YOEBachelors in EE/CS/CE required, 1+ years DFT or ASIC experience preferred. Proficiency in Linux/Windows and scripting (TCL or Python). Strong problem-solving, communication, and ability to work as an individual contributor. Some domestic and international travel.
Linux, Microsoft Windows, TCL, Python, Tessent, Verilog, SystemVerilog, VHDL, ATPG, IEEE 1687
1mo
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Product Test Engineer
Hillsboro, Oregon, United States
OnsiteFull Time
6+ YOEMS with 6 years or BS with 8 years in Electrical/Electronics/Computer Engineering; experience with ATE, IC characterization, test methodologies, RTL/DFT, Verilog/VHDL, Python/C++; strong communication and problem-solving.
Nextest Magnum, Advantest T2K, Teradyne UltraFLEX, Oscilloscope, Pattern Generators, Data Timing Generator, Multimeters, WAT/etest, Verilog, VHDL, Python, C++, Windows, Unix, Microsoft Office
1mo
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Senior Manufacturing Test Engineer
Salem, Oregon, United States
$125k-$163k/yr OnsiteFull Time
7+ YOEBachelor's in EE/SE/Mechatronics,7+ years manufacturing test engineering,expertise in embedded electronics,test automation,DFT/DFM,ECAD reading,Python,protocols (I²C,SPI,UART,CAN,EtherCAT),and hardware troubleshooting.
Python, I²C, SPI, UART, CAN, EtherCAT, Altium, Linux, FreeRTOS, MES, SPC, ECAD, Hardware-in-the-Loop (HIL)
1w
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Senior Electrical Engineer
Portland, Oregon, United States
$130k-$140k/yr OnsiteFull Time
8+ YOEBachelor’s degree in electrical or computer engineering, 8–10+ years’ experience, advanced PCB and EMC design, test equipment expertise, NPI experience, and proficiency with Altium tools.
Altium Designer, Altium 365, Altium Develop, Confluence, Jira, PLM, EVT, DVT, PVT, DFM, DFT, Wirepas, LoRa, oscilloscope, spectrum analyzer, network analyzer, PCB
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Senior Physical Design Engineer
Hillsboro or Redmond or Mountain View or Raleigh or Austin
$120k-$235k/yr HybridFull Time
1+ YOERequires a relevant engineering or computer science degree and 1–5+ years of technical engineering experience; preferred experience includes semiconductor physical design, tape-outs, low-power methods, and signoff workflows.
synthesis, place-and-route, clock construction, CTS, RTL, DFT, RTL to GDS, EMIR, formal equivalence, low-power verification
6d
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Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
Santa Clara or Hillsboro
$136k-$265k/yr OnsiteFull Time
5+ YOEMaster’s degree in electrical engineering, computer engineering, or computer science, or equivalent experience; 5+ years in high-performance semiconductor design; synthesis, timing analysis, floor-planning, and physical design tools expertise.
Verilog, RTL, DFT, ECO
6d
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Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
Santa Clara or Hillsboro
$136k-$265k/yr OnsiteFull Time
5+ YOEMaster’s degree in electrical engineering, computer engineering, computer science, or equivalent; 5+ years in high-performance semiconductor design; synthesis, timing analysis, floor-planning, physical design tools, and ASIC design flow expertise.
Verilog, RTL, DFT, ECO
2w
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SerDes Design and Validation Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Lead system validation of mixed-signal SerDes IP, design and validate analog/mixed-signal circuits, develop analog DFT, create test plans, analyze data, and debug production test and system bring-up issues.
ATE
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Senior ASIC Timing Engineer
Santa Clara or Durham or Austin or Hillsboro
$136k-$265k/yr HybridFull Time
3+ YOEBS in ECE + 5 years or MS + 3 years in timing/STA; hands-on full-chip and sub-chip STA, timing convergence, ECO implementation, physical design optimization, and deep sub-micron modeling.
STA, RTL, DFT, DFX, Formal Verification (FV)