15 eda engineer jobs at 7 companies in Eloy, AZ
2mo
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Technical Staff Engineer - Design
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEBachelors in Electrical/Computer Engineering (Masters preferred), 10+ years experience with Verilog/SystemVerilog/VHDL, chiplet architecture knowledge, advanced-node FinFET design flows, EDA tool and scripting (Python, Tcl, Perl) proficiency, strong analytical and communication skills.
Verilog, SystemVerilog, VHDL, Python, Tcl, Perl, EDA tools, UCIe, FinFET
3w
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Senior Analog Design Engineer
Chandler, Arizona, United States
HybridFull Time
5+ YOE5+ years analog/mixed-signal IC design experience; hands-on CMOS analog circuit design; Cadence/EDA tool proficiency; bachelor’s in electrical-related field; strong analytical, communication, and mentorship skills.
EDA, Cadence
2d
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Sr Digital Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEM.S. in electrical, computer, or related engineering; 10+ years in digital IC design; Verilog/SystemVerilog, EDA tools, synthesis, timing analysis, verification, UVM, and technical leadership experience.
Verilog, SystemVerilog, UVM, Cadence, Synopsys, Siemens EDA
1w
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Technical Staff Engineer - Design
Chandler, Arizona, United States
OnsiteFull Time
12+ YOEBS in electrical engineering with 12+ years experience in pad ring/IO planning, IO cell placement, bump pattern definition, PHY interfaces, EDA tools, scripting (tcl/python), and strong communication and analytical skills.
Orbit IO, ISP, tcl, python, Verilog, System Verilog, SVN, JIRA
2mo
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Engineer II - CAD (Grid Engineer)
Chandler, Arizona, United States
OnsiteFull Time
2+ YOE2.5+ years in Electrical Engineering/CS/HPC; strong Unix/Linux; experience with job schedulers (LSF, SGE, RTDA, SLURM); programming/scripting (csh, Bash, Perl, Python, Tcl, C/C++); EDA tools knowledge (Cadence, Synopsys, Siemens); ML/AI frameworks a plus; strong problem solving and communication.
Unix/Linux, LSF, SGE, RTDA, SLURM, csh, Bash, Perl, Python, Tcl, C/C++, Cadence, Synopsys, Siemens, TensorFlow, LLM
4d
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SOC Design Engineer
Chandler or Cambridge
$198k-$268k/yr HybridFull Time
Experienced electronics engineer with PCB and silicon package co-design expertise, high-speed design, SI/PI analysis, PCB fabrication, EDA tools, and embedded compute systems knowledge.
PCIe, LPDDR, PTH, HDI, VIA, Cadence OrCAD, Cadence Allegro, ANSYS, Siemens EDA
1mo
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Technical Staff Engineer - Design Implementation
Chandler, Arizona, United States
OnsiteFull Time
14+ YOEBS/MS in Electrical Engineering or related with 14+ years SoC implementation experience; expertise in synthesis, UPF, timing closure, hierarchical implementation; hands-on with industry EDA tools and strong cross-functional leadership.
Genus, iSpatial, Design Compiler, Fusion Compiler, Tempus, Primetime, Prime Power, VCLP, RTL architect, Conformal, Formality, UPF
3w
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Senior Engineer I- Design
Chandler, Arizona, United States
OnsiteFull Time
5+ YOEBSEE with 5+ years experience, proficiency in Verilog/SystemVerilog and UVM, Python and TCL scripting, familiarity with Synopsys/Cadence/Siemens EDA tools, and experience with RTL design and verification.
Verilog, SystemVerilog, UVM, Python, TCL, Shell, Synopsys, Cadence, Siemens, AI/ML
3w
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MMIC Design Engineer
Tempe, Arizona, United States
$121k-$190k/yr HybridFull Time
3+ YOEBachelor's/Master's/PhD in EE or related field, 3+ years RF/MMIC design, proficiency with MMIC technologies and EDA tools, experience with S-parameter, load-pull, harmonic balance and noise analysis.
Keysight ADS, Cadence Virtuoso, AWR Microwave Office, HFSS, CST Microwave Studio, Python, MATLAB, LabVIEW
1w
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Principal Analog Design Engineer - DC DC Architect
Chandler, Arizona, United States
OnsiteFull Time
12+ YOE5+ MgmtM.S. or Ph.D. in electrical engineering required; 12+ years analog or mixed-signal IC design experience and 5+ years technical leadership or architecture experience. Requires DC-DC, PMIC, transistor-level design, EDA, and English skills.
Cadence, Synopsys, Siemens EDA
3mo
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Senior Engineer I - Physical Design
Chandler, Arizona, United States
OnsiteFull Time
5+ YOE5+ years in physical design; place-and-route; low-power flows; EDA tools; scripting; Verilog/VHDL; strong debugging and communication.
Innovus, Fusion Compiler, Calibre, Redhawk, Starrcxt, Verilog, VHDL, TCL, PERL, Shell
1w
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Technical Staff Engineer - Design (FPGA Fabric)
San Jose or Chandler
$91k-$232k/yr OnsiteFull Time
12+ YOEBachelor's degree and 12+ years in custom FPGA fabric or memory circuit design. Requires SPICE, EDA, scripting, Verilog, simulation, yield, reliability, power, and cross-functional design expertise.
SPICE, Verilog, Solido, Monte Carlo
2mo
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Staff Engineer, Mixed Signal Design Engineering
Chandler or Wilmington
$125k-$181k/yr OnsiteFull Time
5+ YOEExpert mixed-signal IC design experience, system-level integration, verification strategy, EDA tool mastery (SPICE, MATLAB, Cadence), leadership of complex projects; MSEE or PhD preferred.
SPICE, MATLAB, Cadence Design Suite
2w
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ESD & CAD Design Manager
Chandler, Arizona, United States
$129k-$207k/yr OnsiteFull Time
12+ YOE3+ MgmtMS in Engineering and 12+ years ESD & CAD experience with 3+ years management; deep ESD knowledge; proficiency with CAD platforms, scripting (Perl, Python) and EDA tools; strong leadership and communication.
Cadence Virtuoso, Synopsys Primetime, Ansys Seascape, Redhawk, Totem PathFinder, Verilog, Calibre, Perl, Python, Skill, TCL
4d
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Principal PCB - Package co-design Architect
Chandler, Arizona, United States
$250k-$338k/yr HybridFull Time
Deep SoC and embedded compute expertise; high-speed I/O, PCB and package co-design, SI/PI, EDA tools, fabrication, routing, manufacturability, and cross-functional architecture experience required.
PCIe, LPDDR5, LPDDR6, CSI, DSI, FPGA, PMIC, Cadence OrCAD, Cadence Allegro, ANSYS, Siemens EDA