14 eda engineer jobs at 9 companies in New York City, NY

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FPGA Engineer
Amsterdam or Chicago or London or New York City or Singapore
OnsiteFull Time
Headlands Technologies
Headlands Technologies: A global proprietary trading firm utilizing quantitative algorithms.
Professional FPGA/ASIC design and verification experience; SystemVerilog/Verilog/VHDL and C++; familiarity with EDA tools and scripting (TCL, Python, Bash); university degree in EE/CS/CE or related.
SystemVerilog, Verilog, VHDL, C++, TCL, Python, Bash, EDA
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Forward Deployed AI Engineer
New York City or San Francisco
$180k-$325k/yr HybridFull Time
Normal Computing
Normal Computing: Building probabilistic AI and thermodynamic computing for semiconductor design.
Experience deploying ML systems in customer environments; strong Python; knowledge of embedded hardware/EDA; ability to work with silicon design workflows; familiarity with ML deployment and evaluation.
Python, Distributed Systems, ML Stack, EDA tools
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Anthropic
Anthropic: Developing safe and reliable artificial intelligence systems.
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
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Technical Staff Engineer - Applications
San Jose or Addison or Allentown or Hauppauge
$91k-$232k/yr HybridFull Time
Microchip Technology
Microchip TechnologyNasdaq: MCHP: Manufacturer of microcontrollers, analog, and mixed-signal integrated circuits.
12+ YOEBachelors in EE/Comp Eng/Science required (Masters preferred); 12+ years FPGA architecture/design experience; 5+ years lab equipment use; expert VHDL/Verilog and C; experience with Libero/Vivado/Quartus, Linux, Keil/IAR/Eclipse, EDA tools; strong communication.
Libero, Vivado, Quartus, Keil, IAR, Eclipse, Linux, C, VHDL, Verilog, RISC-V, EDA tools, Oscilloscopes, Signal analyzers
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Application Engineering-Bachelor’s or Master’s degree in Electronics, Electrical Engineering
Sofia or Dresden or Singapore or New York City or Vermont
HybridFull Time
GlobalFoundries
GlobalFoundriesNASDAQ: GFS: Semiconductor foundry providing chip design and fabrication services.
0+ YOETechnical degree in electronics/electrical engineering required; 0–4 years relevant experience depending on degree. Customer-facing semiconductor application support, EDA/PDK exposure, strong communication and problem-solving skills, English proficiency.
PDKs, EDA tools
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PMTS, A&D Field Application Eng
Austin or Santa Clara or Richardson or New York City or Malta
$145k-$236k/yr OnsiteFull Time
GlobalFoundries
GlobalFoundriesNASDAQ: GFS: Manufacturer of semiconductors and provider of wafer fabrication services.
Bachelor's in electrical engineering (or equivalent), strong IC design/tapeout/process experience, working knowledge of EDA tools, ability to obtain SECRET clearance, U.S. work-authorization requirement, domestic/international travel up to 20%.
EDA
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PMTS Field Application Eng - Power GaN & BCD
Santa Clara or Richardson or Austin or New York City or Malta
$145k-$236k/yr OnsiteFull Time
GlobalFoundries
GlobalFoundriesNASDAQ: GFS: Manufacturer of semiconductors and provider of wafer fabrication services.
15+ YOEBachelor's in electrical engineering (Masters/PhD preferred), minimum 15 years semiconductor design/tapeout experience, IC design flow and EDA tool knowledge for BCD and GaN, technical program management, strong communication; travel up to 20%.
EDA tools
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Sr. Analog IC Design Engineer - IVR Architecture Team (Remote)
New York, New York, United States
$135k-$170k/yr HybridFull Time
Ferric
Ferric: Developing on-chip voltage regulator technology for advanced electronics.
MSEE with analog design experience; strong control theory, switching converter, CMOS analog, custom IC flows; experience with high-frequency IVR design, verification, and bench validation; proficiency in listed EDA tools and languages.
Cadence Virtuoso, LVS, DRC, SPICE, parasitic extraction, electromagnetics simulators, Verilog, Verilog-AMS, Python, Perl, Tcl, Cadence Skill, MATLAB
3d
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Founding Engineer
New York City, New York, United States
$150k-$220k/yr OnsiteFull Time
Clera
Clera: AI talent agent matching professionals with high-growth startup roles
4+ YOERequires 4+ years shipping production software, production LLM agent workflows, strong Python and backend or ML systems engineering, observability, evaluation, testing, on-call operations, and customer-site travel.
Python, CAD, CAE, PLM, LLM, EDA
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ASIC Technical Lead- DFT
San Jose or New York City or New York or Washington or Illinois or United States or Canada
$211k-$305k/yr HybridFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
10+ YOEBachelor's or Master's in Electrical/Computer Engineering with 10+ years experience; expertise in JTAG, scan and BIST architectures, ATPG and EDA toolsets (TestMax, Tetramax, Tessent, PrimeTime); SystemVerilog/Verilog and post-silicon debug experience.
JTAG, ATPG, TestMax, Tetramax, Tessent, PrimeTime, System Verilog, Verilog
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Infrastructure Software Engineer
New York City or Copenhagen or London or San Francisco
$185k-$285k/yr HybridFull Time
Normal Computing
Normal Computing: Building probabilistic AI and thermodynamic computing for semiconductor design.
4+ YOE4+ years in infrastructure or backend systems; strong backend engineering, APIs, distributed systems, observability; practical Docker/Kubernetes and persistence (Postgres, Redis) experience; ownership and cross-team communication.
Docker, Kubernetes, Postgres, Redis/Valkey, object storage, EDA
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DFT Technical Leader
San Jose or Austin or New York City or New York or Washington or United States or Canada
$184k-$264k/yr HybridFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
10+ YOEBachelor's or Master's in Electrical/Computer Engineering, 10+ years experience in DFT, Jtag/Scan/BIST, ATPG and EDA tools, gate-level simulation and post-silicon validation experience.
Jtag, Scan, BIST, ATPG, TestMax, Tetramax, Tessent, PrimeTime, VCS, P1687, Verilog, System Verilog
6d
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Analog Layout Designer (TEMPORARY POSITION)
Burlington or New York City or California
$100/hr HybridTemporary
Butterfly Network
Butterfly NetworkNYSE: BFLY: Handheld whole-body ultrasound scanners powered by semiconductor technology.
Expertise in precision analog circuit layout, CMOS design principles, low- and high-voltage designs, parasitic extraction, LVS, DRC, and Cadence EDA tools; must be authorized to work in the US without sponsorship.
Cadence EDA, TSMC 130nm BCD, CMOS, LVS, DRC
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Technical Recruiter, ASICs
New York City or Palo Alto or London or Copenhagen or Seoul
$150k-$195k/yr HybridFull Time
Normal Computing
Normal Computing: Building probabilistic AI and thermodynamic computing for semiconductor design.
4+ YOE4+ years full-cycle technical recruiting with direct ASIC/silicon/semiconductor experience; track record closing senior engineers; strong technical literacy in EDA/AI silicon; advanced Ashby/ATS proficiency.
Ashby