13 eda jobs at 6 companies in Loveland, CO
1mo
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EDA Customer Success Application Engineer
Santa Rosa or Colorado Springs or Loveland
$97k-$162k/yr RemoteFull Time
5+ YOEB.S. in Electrical Engineering or equivalent with 5+ years experience; proficiency with EDA tools (ADS, SystemVue, etc.), troubleshooting, Python, strong communication, and U.S. person status.
ADS, SystemVue, GoldenGate, Genesys, IC-CAP, MBP, MQA, Python
1mo
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EDA Customer Success Application Engineer
Santa Rosa or Colorado Springs or Loveland
$97k-$162k/yr OnsiteFull Time
5+ YOEB.S. in Electrical Engineering or equivalent with 5+ years experience; background in RF/microwave, RFIC, high-speed digital or EDA support; proficiency with ADS/SystemVue/EM simulation; Python experience; strong communication.
ADS, SystemVue, EM simulation, GoldenGate, Genesys, IC-CAP, MBP, MQA, Python
4d
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Sr. Silicon Design Engineer
Fort Collins, Colorado, United States
$106k-$152k/yr OnsiteFull Time
1+ YOEMaster’s degree in electrical engineering, computer engineering, computer science, or related field; 1 year of related experience in ASIC, CMOS, physical design, EDA tools, and Verilog.
Verilog, ASIC, EDA, CMOS
6d
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CPU Core Physical Design Thermal Modeling Lead
Santa Clara or Austin or Fort Collins or Boxborough
$175k-$300k/yr HybridFull Time
Requires a bachelor's or master's degree in computer or electrical engineering, strong physical design and EDA experience, SoC/IP design knowledge, package modeling familiarity, and scripting and flow automation expertise.
EDA, SoC, IP
2d
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SI/PI Tech Project Manager
San Jose or Fort Collins
OnsiteFull Time
12+ YOE3+ MgmtBSEE and 12+ years in ASIC and system signal/power integrity for high-speed SerDes, plus 3+ years of leadership or management experience. Requires package, PCB, EDA, lab, and project management expertise.
SerDes, Optics, RF, Microwave, ADC, DAC, HBM, DDR5, EDA, MCM
2mo
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Senior Custom ASIC Engineering Lead
San Jose or Fort Collins or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOEExtensive ASIC physical design and STA experience, multiple tape-outs in advanced nodes, EDA tool and scripting (Tcl, shell) proficiency, knowledge of low-power design, and ability to manage customer ASIC programs. Bachelors+12 yrs or Masters+10 yrs required.
EDA, Tcl, Shell, Verilog
3mo
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Electronics Engineer II
Westminster, Colorado, United States
$102k-$136k/yr OnsiteFull Time
2+ YOEBachelor's in Electrical Engineering; 2+ years hardware development; PCB layout; EDA tools; lab instrumentation; strong communication.
Altium, LTSpice, Oscilloscope, Spectrum Analyzer
2w
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VP, Technical Sales
Austin or Boulder or Costa Mesa or San Diego or Wilsonville
$248k-$472k/yr HybridFull Time
Extensive EDA and semiconductor industry experience with proven commercial leadership, ability to build global teams, drive new business growth, and align technical sales with portfolio and regional priorities.
1w
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Senior ASIC Design Engineer
Boulder or Austin
$140k-$175k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOERequires a master's or PhD in electrical engineering or related field, 5+ years of hardware engineering experience, a complete ASIC cycle, DSP, RTL/SystemVerilog, FPGA, and EDA tool expertise.
SystemVerilog, RTL, FPGA, Cadence, Synopsys, Siemens EDA
1w
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Senior Product Planning Engineer - Simulation, Security, and Deployment
San Jose or Longmont
$144k-$246k/yr HybridFull Time
Deep expertise in UVM, SystemVerilog, RTL simulation, formal methods, and multi-language simulation; experience with EDA product roadmaps, AI agents, enterprise deployment, licensing, and executive communication.
AMD Vivado, UVM, SystemVerilog, HDL, VHDL, Verilog, Vivado Simulator, Xcelium, Questa, Riviera, AI agents, copilots
2w
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ASIC Physical Design Engineer
Boulder or Beaverton or Louisville
HybridFull Time
5+ YOEBS in Electrical Engineering, 5+ years ASIC physical design experience from RTL to GDS, proficiency with Cadence/Synopsys/Siemens EDA, static timing analysis, signoff checks, and scripting (Tcl, Python, Perl, shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
2w
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ASIC Physical Design Engineer
Boulder or Beaverton
$149k-$277k/yr HybridFull Time
5+ YOEBS in Electrical Engineering,5+ years ASIC/SoC physical design experience from RTL to GDS,static timing and signoff expertise,proficiency with Cadence/Synopsys/Siemens EDA and scripting (Tcl,Python,Perl,shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
2mo
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Senior Custom ASIC Engineering Lead
San Jose or Fort Collins or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE10+ years semiconductor ASIC experience, multiple tape-outs, hands-on physical design/STA/DFT experience, Tcl/shell/Verilog scripting, knowledge of low-power design and PPA tradeoffs; Bachelor's or Master's degree required.
EDA, Tcl, Shell, Verilog