4w
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Emulation Engineer / Emulation Platform Engineer
Austin, Texas, United States
$154k-$231k/yr OnsiteFull Time
2+ YOEBachelor's (with 4+ years) / Master's (3+ years) / PhD (2+ years) in EE/CS/CE or related, 2+ years microprocessor design experience, proficiency with emulation platforms (Veloce/Palladium/ZeBu), SystemVerilog, Git, and scripting (Python/Tcl/Shell).
Veloce, Palladium, ZeBu, Angel debug monitor, Git, SystemVerilog, SystemVerilog DPI, RTL, Python, Tcl, Shell, UVM, LSF, Slurm, Zephyr, FreeRTOS, embedded Linux
1mo
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Principal Engineer, Emulation
Austin, Texas, United States
$221k-$312k/yr HybridFull Time
15+ YOE15+ years experience with Bachelor's (or equivalent); expertise in emulation, FPGA prototyping, System Verilog, RTL, SoC integration, emulation performance optimization, automation, and technical leadership.
System Verilog, RTL, FPGA
1mo
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Senior Emulation Methodology Engineer
Austin, Texas, United States
HybridFull Time
Technical leader for emulation/prototyping methodology with experience across emulation platforms, RTL/verification/firmware, System Verilog/C++/Perl/Python proficiency, and CPU/GPU protocol knowledge; bachelor’s or master’s in engineering required.
Veloce, Palladium, Protium, Zebu, HAPS, System Verilog, C++, Perl, Python, Verdi, Visualizer
1mo
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Senior Applications Engineer - Emulation
Austin or San Diego or Costa Mesa or Wilsonville
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/emulation and prototyping of electronics chips and systems; BS or MS in EE, CE, CS or related fields.
Emulation platforms (Veloce, Palladium, Zebu), SystemVerilog, Verilog, VHDL, SystemC, C, C++, Perl, Python, XML, JSON
3mo
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Staff Engineer, Emulation Technical Lead
Austin, Texas, United States
$100k-$500k/yr HybridFull Time
5+ YOEStrong background in CPU verification, emulation, and debug; fluent in Verilog/SystemVerilog; technical leader with mentoring experience.
Verilog, SystemVerilog, Zebu emulation platforms
3mo
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Graphics Emulation Test Bench and Infrastructure Architect
Austin, Texas, United States
OnsiteFull Time
10+ YOEBS plus 10 years in hardware/software verification; experience with PCIe/AXI, DPI/transactors, RTL, and multiple programming languages.
PCIe, AXI, DPI/Transactors, SystemVerilog, Verilog, C/C++, Python, Perl, Ruby
1mo
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Senior Field Security Applications Engineer
Campbell or Austin or United States
$140k-$190k/yr FieldFull Time
5+ YOE5+ years SoC design and verification experience with Verilog/VHDL/SystemVerilog, RTL simulation/emulation tools, strong presentation skills, willingness to travel, US citizenship required.
Verilog, VHDL, SystemVerilog, RTL Simulation, Emulation, Synopsys, Cadence, Siemens, Cycuity Radix, Cycuity HW, FPGA-based Prototyping
3d
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System Software Engineer, Profiler - GPU
Austin or Santa Clara or California or Texas
$152k-$288k/yr HybridFull Time
5+ YOEBS in EE/CS (or equiv) with 5+ years (MS with 2+ or Ph.D. acceptable). Strong C/C++, Python, low-level assembly, hardware pipeline knowledge, simulator/emulator and performance analysis experience.
Nsight, CUDA, GPU Assembly, emulators, simulators, C, C++, Python, OpenCL, DirectX12, OpenGL, Vulkan, Metal, PyTorch, JAX
1w
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Principal Design Verification Engineer – CPU Subsystem Power Management
Austin or Santa Clara
OnsiteFull Time
12+ YOEBS/MS/PhD in EE/CE/CS,12+ years CPU/SoC functional verification with strong CPU-subsystem power-management expertise, SystemVerilog and Python skills, experience with formal/emulation and subsystem signoff, strong communication.
SystemVerilog, Python, formal, emulation
1mo
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Principal Silicon Design Verification Engineer
Mountain View or Austin or Redmond or Raleigh or Hillsboro
$143k-$275k/yr HybridFull Time
3+ YOEDegree in EE/CE/CS (or equivalent) with multi-year technical experience depending on degree; expertise in C/C++, SystemVerilog, UVM, pre-silicon verification, scripting (Python/Ruby/Perl), FPGA/emulation, build flows, and hardware debug; must pass Microsoft Cloud Background Check and meet export-control citizenship/residency requirements.
C, C++, SystemVerilog, UVM, Python, Ruby, Perl, HAPS, Xilinx, Makefiles, linker scripts, assembly, AMBA (AXI/AHB/APB), JTAG, SPI, I2C/I3C, USB, logic analyzers, oscilloscopes, multimeters, FPGA, emulation
2w
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Senior Firmware Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBS/MS in EE or Computer Engineering required; 5+ years firmware verification experience in pre-silicon; SystemVerilog, C, Python/Perl skills; familiarity with RTL, emulation, and lab test equipment.
SystemVerilog, UVM, C, Python, Perl, RTL, FPGA, QEMU, SimVision, Verdi, oscilloscopes, power supplies, logic analyzers
1mo
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Senior ASIC Design Engineer - Terawave
San Diego or California or Austin or Kent or Texas or Washington
$230k-$323k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in Electrical Engineering (or related), 8+ years experience in pre- and post-silicon SoC verification, strong SystemVerilog and DSP knowledge, emulation/FPGA/silicon bring-up experience, and verification methodology expertise.
SystemVerilog, MATLAB, SystemC, C, FPGA
1mo
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Principal Applications Engineer
Austin, Texas, United States
$160k-$240k/yr RemoteFull Time
Extensive emulation platform experience, strong HDL and verification methodology knowledge (Verilog/SystemVerilog/VHDL, UVM/OVM), SoC/ASIC architecture expertise, scripting (Python/Perl/TCL), customer engagement and mentoring skills.
SynopsysZeBu, Mentor Veloce, Cadence Palladium, Verilog, SystemVerilog, VHDL, UVM, OVM, Python, Perl, TCL
3mo
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Design Verification Engineer - Interface IP
Austin or San Jose
$150k-$275k/yr OnsiteFull Time
5+ YOE5+ years in design verification; SystemVerilog/UVM; experience with IP interfaces (PCIe, Ethernet, AXI/AMBA, ARM/ARC); able to collaborate across RTL, software, and emulation; thrives in a fast-paced startup.
SystemVerilog, UVM, PCIe, Ethernet, AXI/AMBA, ARM/ARC CPUs
2mo
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IP Verification Engineer
Austin, Texas, United States
HybridFull Time
Several years of industry RTL verification experience, strong SystemVerilog/UVM skills, RTL testbench and TLM modeling, HW emulation experience, scripting (TCL/Python/Perl), familiarity with SerDes/PCIe/ARM/DSP/Ethernet and AMBA protocols, and BS/MS in EE/CE.
SystemVerilog, UVM, TLM, SerDes, PCIe, ARM, DSP, Ethernet, TCL, Python, Perl, C, Assembly, Linux, GIT, LSF, AMBA, APB, AXI, ACE-Lite, CHI
3w
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's in CS/CE or equivalent, 8+ years SystemVerilog/UVM or C/C++ verification, IP/SoC verification experience, EDA and scripting (Python, TCL, Perl, Shell), experience with assertions, formal or emulation.
SystemVerilog, UVM, OVM, C, C++, Python, TCL, Perl, Shell
1mo
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Post-Silicon Systems Validation Engineer, Annapurna Labs
Austin, Texas, United States
$144k-$194k/yr OnsiteFull Time
3+ YOE3+ years design or architecture experience, programming proficiency (Python/C/C++/Rust/Go/Lua), strong computer architecture knowledge, ML fundamentals, firmware/firmware-debug experience, familiarity with RTL simulation, emulation and post-silicon validation; Bachelor's in CS/engineering/math or equivalent.
Python, Lua, C, C++, Rust, Go, AWS services, PyTorch, JAX, SystemVerilog, UVM, VCS, Questa, Xcelium, Palladium, Zebu, Veloce, oscilloscope, logic analyzer, protocol analyzer
1mo
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Post Silicon Engineer (eInfochips)
Cupertino or Austin or Bedford
OnsiteFull Time
8+ YOE8+ years experience in silicon validation, strong programming (Python, Lua, C/C++, Rust, Go), computer architecture and chip/system validation, cloud CI/CD, firmware testing, Linux/Git, EDA simulation/emulation and hardware debug experience.
Python, Lua, C/C++, Rust, Go, SystemVerilog/UVM, VCS, Questa, Xcelium, Palladium, Zebu, Veloce, Linux, Git, CI/CD, oscilloscope, logic analyzer, protocol analyzer
3w
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Validation Engineer (780324)
Austin, Texas, United States
HybridFull Time
10+ YOE10+ years development experience in C/C++ and Python with hardware validation focus; experience with Git, Unix/Linux, ASIC validation, lab debugging, and technical leadership/mentoring.
C, C++, Python, Git, IDEs, Unix, Linux, protocol analyzers, oscilloscopes, hardware emulators
2mo
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Member of Technical Staff, Hardware, Design Verification Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOE5+ years industry experience, BS in EE/CE/CS, deep SystemVerilog and UVM experience, verification methodology expertise, familiarity with emulation/prototyping and formal methods, strong collaboration and debugging skills.
SystemVerilog, UVM, ZeBu, HAPS, Palladium, Protium, Python, Perl, Bash, TCL, SVA, Jasper, VC Formal, AXI, CHI