13 emulation prototyping senior engineer jobs at 9 companies in United States
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Senior Systems Prototyping and Emulation Engineer
Santa Clara, California, United States
$168k-$311k/yr OnsiteFull Time
6+ YOEBS in Electrical/Computer Engineering with 8+ years or MS with 6+ years in FPGA prototyping and hardware emulation; strong FPGA/prototyping tools, Verilog/SystemVerilog, PCIe/CXL/NVLINK, lab debug, and emulation platforms.
Synopsys ProtoCompiler, Synplify Premier, Xilinx Vivado, Synopsys ZeBu, Siemens Veloce, VCS, Verdi, GDB, Identify, ChipScope, Oscilloscopes, Logic analyzers, DPI/PLI/SystemC
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Senior Systems Prototyping and Emulation Engineer
Santa Clara, California, United States
$168k-$311k/yr OnsiteFull Time
8+ YOEBS with 8+ years or MS with 6+ years in FPGA prototyping or hardware emulation; experience with RTL, FPGA flows, emulation platforms, C/C++, Verilog/SystemVerilog, digital design, and high-speed validation.
Synopsys ProtoCompiler, Synplify Premier, Xilinx Vivado, Synopsys ZeBu, Siemens Veloce, VCS, Verdi, GDB, Verilog, SystemVerilog, Identify, ChipScope, C, C++, DPI, PLI, SystemC, Perl, Tcl, Python, Synopsys HAPS, shell
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Senior Systems Prototyping and Emulation Engineer
Santa Clara, California, United States
$168k-$311k/yr OnsiteFull Time
8+ YOEBS in EE/CE (8+ yrs) or MS (6+ yrs) or equivalent experience; proven FPGA prototyping and hardware emulation expertise; experience with Synopsys ProtoCompiler, Synplify Premier, Xilinx Vivado, Synopsys ZeBu/Siemens Veloce; Verilog/SystemVerilog and C/C++ skills.
Synopsys ProtoCompiler, Synplify Premier, Xilinx Vivado, Synopsys ZeBu, Siemens Veloce, Synopsys HAPS, VCS, Verdi, GDB, Verilog, SystemVerilog, C/C++, SystemC, DPI, PLI, Perl, shell, Tcl, Python, Identify, ChipScope, oscilloscope, logic analyzer
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Senior Emulation Engineer
San Jose or United States
$138k-$206k/yr OnsiteFull Time
5+ YOERequires a bachelor's degree with 5+ years, master's with 3+ years, or PhD with 0+ years, plus 5+ years in FPGA prototyping and hardware emulation, SoC validation, and Verilog/SystemVerilog.
Cadence Palladium, Synopsys ZeBu, Siemens Veloce, Synopsys HAPS, Cadence Protium, SCE-MI, PCIe, DDR/HBM, AXI/CHI, Ethernet, Verilog, SystemVerilog, Tcl, Python, Perl, Artificial Intelligence (AI)
2mo
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Senior Emulation Methodology Engineer
Austin, Texas, United States
HybridFull Time
Technical leader for emulation/prototyping methodology with experience across emulation platforms, RTL/verification/firmware, System Verilog/C++/Perl/Python proficiency, and CPU/GPU protocol knowledge; bachelor’s or master’s in engineering required.
Veloce, Palladium, Protium, Zebu, HAPS, System Verilog, C++, Perl, Python, Verdi, Visualizer
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Senior ICE Emulation Design Engineer
San Jose, California, United States
$150k-$190k/yr OnsiteFull Time
7+ YOE7+ years in prototyping, emulation, SOC design/validation; strong problem solving, scripting skills; experience with high/low-speed interfaces.
PCIe, Ethernet, USB, I2C, SPI, UART, Python, Perl, TCL
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Senior Applications Engineer - Emulation
Austin or San Diego or Costa Mesa or Wilsonville
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/emulation and prototyping of electronics chips and systems; BS or MS in EE, CE, CS or related fields.
Emulation platforms (Veloce, Palladium, Zebu), SystemVerilog, Verilog, VHDL, SystemC, C, C++, Perl, Python, XML, JSON
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Senior FPGA Design Verification Engineer
Sunnyvale, California, United States
$152k-$257k/yr OnsiteFull Time
Advanced knowledge of HVL/UVM and HDL (SystemVerilog, Verilog); experience with coverage-driven verification, constrained-random testing, testbench development, scripting (Perl/Python); experience with emulation/FPGA prototyping, formal methods and ML-assisted verification is a plus.
HVL, UVM, SystemVerilog, Verilog, Perl, Python, FPGA, Emulation, Formal
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Senior Systems Software Engineer, Data Center Platform Enablement
Santa Clara, California, United States
$184k-$357k/yr OnsiteFull Time
8+ YOE8+ years experience in computer system and firmware architecture for servers; experience with CPLD/FPGA/RTL, low-level interfaces (I2C/SPI/PCIe/JTAG), embedded Linux, C/C++, bash/python, QEMU/emulation, and prototype debug.
C, C++, bash, python, QEMU, CPLD, FPGA, RTL, I2C, SPI, PCIe, JTAG, SBIOS, BMC, embedded Linux, NVLink, NVMe
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Sr Principal Design Engineer
San Jose, California, United States
$154k-$286k/yr OnsiteFull Time
7+ YOEBS+10 years or MS+7 years experience in digital design and system-level verification; expertise in emulation, FPGA prototyping, SystemVerilog/Verilog or C/C++; experience with high-speed protocols (e.g., PCIe, CXL), debugging, and customer engagement.
Palladium, Protium, SystemVerilog, Verilog, C, C++
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Member of Technical Staff, Hardware, Design Verification Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOE5+ years industry experience, BS in EE/CE/CS, deep SystemVerilog and UVM experience, verification methodology expertise, familiarity with emulation/prototyping and formal methods, strong collaboration and debugging skills.
SystemVerilog, UVM, ZeBu, HAPS, Palladium, Protium, Python, Perl, Bash, TCL, SVA, Jasper, VC Formal, AXI, CHI
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Architect - FPGA Design, AXI/ UCIe Protocol
Sunnyvale, California, United States
$208k-$312k/yr OnsiteFull Time
12+ YOEExtensive FPGA/RTL design experience; 12+ years; expertise in PCIe, UCIe, AXI, CXL; emulation/prototyping; RTL/firmware debugging across hardware and software.
Verilog, SystemVerilog, FPGA, ZeBu, HAPS, Veloce, Palladium, In-Circuit Emulation, Direct-ICE
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AE Manager
Fremont or Santa Clara
$167k-$334k/yr HybridFull Time
10+ YOEBachelor's degree in engineering or computer science and 10+ years of relevant experience. Requires technical sales leadership, hardware emulation, FPGA prototyping, DFT, low-power verification, communication, and team leadership.
UPF, FPGA, ASIC, ATPG, MBIST, LBIST, Microsoft?