20 engineer digital design engineering jobs at 9 companies in Eloy, AZ
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Principal Engineer, Digital Design Engineering
Chandler or Wilmington
$152k-$227k/yr OnsiteFull Time
12+ YOE12+ years in digital design engineering with SoC architecture expertise, multi-domain technical mastery, ability to define technical strategy, lead architecture, drive innovation, mentor engineers, and engage with customers and industry.
2d
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Senior Digital Design Engineer
Vancouver or Chandler or San Francisco
$150k-$200k/yr HybridFull Time
6+ YOEBachelor's or master's degree in electrical or computer engineering, 6+ years of digital IC design experience, and hands-on Verilog or SystemVerilog RTL development for complex SoCs or ASICs.
Verilog, SystemVerilog, Synopsys, Cadence, SDC, UPF, CPF
1w
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Sr Digital Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEM.S. in electrical, computer, or related engineering; 10+ years in digital IC design; Verilog/SystemVerilog, EDA tools, synthesis, timing analysis, verification, UVM, and technical leadership experience.
Verilog, SystemVerilog, UVM, Cadence, Synopsys, Siemens EDA
1mo
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Staff Digital Design Engineer
Chandler, Arizona, United States
HybridFull Time
11+ YOE>10 years digital design experience, degree in EE/CE/CS or related, fluent Verilog/SystemVerilog, ASIC methodology knowledge, Lint/CDC/RDC experience, RTL and gate-level debug, English proficiency, travel readiness.
Verilog, SystemVerilog, Lint, CDC, RDC, UPF, UVM, AMBA, I2C, STA
3mo
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Senior Hardware Design Engineer - Space
Tempe, Arizona, United States
$156k-$246k/yr OnsiteFull Time
15+ YOEExperience leading digital hardware designs (FPGA) and embedded systems; lead cross‑functional teams; proficient with lab equipment; BS in Electrical Engineering; US citizenship; travel up to 10%.
Xilinx FPGA, Microchip RTAX/RTSX/ProASIC, Synplify, ModelSim, FPGA toolchains, Lab equipment
3w
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FPGA Digital Engineer - 2
Chandler, Arizona, United States
$87k-$131k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE or related with 2 years experience (or Master's); ability to obtain DoD Secret clearance; FPGA design experience (VHDL/Verilog), Vivado, simulation and verification skills; familiarity with Xilinx devices and digital interfaces.
Vivado IDE, Questa/ModelSim, Vitis Unified IDE, AMD Xilinx FPGAs and SoCs, VHDL, Verilog, C, C++, OSVVM, UVM
3d
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Principal Engineer- Design (FPGA)
Chandler, Arizona, United States
OnsiteFull Time
10+ YOE10+ years in FPGA or digital design; expertise in RTL, Verilog/SystemVerilog, simulation, synthesis, timing, implementation, multi-clock systems, board bring-up, lab debugging, and technical documentation.
Verilog, SystemVerilog, QuestaSim, ModelSim, AMD/Xilinx Vivado, TCL, Python, Perl, Linux, C++, RUST, Perforce, Git, DesignSync, FPGA, RTL
3w
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Principal FPGA Digital Engineer - 3
Chandler, Arizona, United States
$108k-$162k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE (or MS/PhD) with relevant FPGA/SoC design experience, expertise in VHDL/Verilog and Xilinx toolflow, static timing analysis, bus interfaces, simulation/verification, and ability to obtain DoD Secret clearance.
VHDL, Verilog, AMD Xilinx FPGAs, Vivado IDE, Vitis Unified IDE, Questa/ModelSim, OSVVM, UVM, AXI4, Ethernet, PCIe, UART, SDLC, DDR3, DDR4, DDR5, logic analyzer, oscilloscope, C, C++
3w
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Electrical Engineer / Counter-UAS
Gilbert, Arizona, United States
OnsiteFull Time
5+ YOEBachelor's in EE,5+ years electrical design and system integration,experience with power distribution,analog/digital circuitry,PCB tools,EMI/EMC,communication protocols,and ability to obtain security clearance.
Altium, OrCAD, KiCad, UART, SPI, I2C, Ethernet, CAN
3d
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BIM Coordinator
Chandler, Arizona, United States
HybridFull Time
7+ YOERecognized degree or diploma in architecture, engineering, construction management, design technology, information management, or related field, plus typically 7+ years of BIM, Revit, digital delivery, design, engineering, or construction technology experience.
Autodesk Revit, BIM 360, Autodesk Construction Cloud (ACC), Navisworks, Dynamo, Microsoft Power BI, ISO 19650