1w
Save
Mark Applied
Hide
Senior Principal ASIC FPGA Engineer
Boise or United States
$191k-$212k/yr HybridFull Time
10+ YOEBachelor's (or Master's) in ECE or related plus 8–10+ years ASIC/FPGA experience, DoD Secret clearance, RTL and timing-closure expertise, FinFET and foundry flow experience, JIRA and Microsoft Office proficiency.
JIRA, Microsoft Office
2mo
Save
Mark Applied
Hide
FPGA Engineer (Idaho, Boise)
Boise, Idaho, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
RTL, C/C++, Python, VHDL, Verilog, Tcl; hardware security; Xilinx; Vivado; IP core development; system integration; cryptography; hardware/software co-design; experience with simulation and verification tools; ability to obtain/maintain U.S. government security clearance.
C/C++, Python, VHDL, Verilog, Tcl, Vivado, Questa, Quartus Prime, GHDL, Xilinx, AXI, Avalon, ACE, IP core design, HDL
2w
Save
Mark Applied
Hide
Senior DRAM Security Test Engineer
Boise, Idaho, United States
OnsiteFull Time
BS in EE/CE or equivalent, FPGA development with Verilog/SystemVerilog/VHDL, Xilinx Vivado or Intel Quartus, Python/C++ skills, hardware/software integration, EM automation, and experience with AI-assisted development tools.
Verilog, SystemVerilog, VHDL, Xilinx Vivado, Intel Quartus, Python, C++, Claude, PCIe, AXI, DMA, JEDEC, ATE
3d
Save
Mark Applied
Hide
Lead ASIC Digital Design Engineer
Annapolis Junction or Telework or Boise or Salt Lake City or Bloomington
$177k-$187k/yr RemoteFull Time
8+ YOE8+ years ASIC/FPGA RTL design experience, ASIC tape-out and timing-closure experience, familiarity with FinFET nodes and commercial foundry flows, EDA tool and JIRA proficiency, strong RTL and microarchitecture skills.
JIRA, Microsoft Office