2mo
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Junior Engineer, FPGA
Princeton, New Jersey, United States
$60k-$62k/yr OnsiteFull Time
FPGA design with Verilog/VHDL or HLS; testbench development; target/retarget FPGA designs; knowledge of Verilog, VHDL, SystemVerilog and C; experience with timing closure and Xilinx boards; document design data sheets.
Verilog, VHDL, SystemVerilog, C, Xilinx tools, FPGA
2mo
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FPGA Engineer
Exton, Pennsylvania, United States
OnsiteFull Time
2+ YOEBachelor's in Electrical Engineering; 2+ years FPGA/ASIC in regulated environments; proficient in Verilog/VHDL; Xilinx Vivado; DO-254 familiarity; hardware debugging; cross-functional collaboration
Verilog, VHDL, Xilinx Vivado, RTL simulation, ModelSim/Questa, DO-254 knowledge, I2C, SPI, JTAG, Ethernet, PCIe
1w
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FPGA Engineer - Control Systems
Princeton, New Jersey, United States
$150k-$235k/yr OnsiteFull Time
Experienced in FPGA/ASIC digital logic design and verification, RTL and low-latency firmware for multi-domain clock systems; familiarity with Xilinx/AMD RFSoC platforms preferred.
RTL, FPGAs, ASICs, Xilinx, AMD, RFSoC
2mo
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Junior Engineer, FPGA
Princeton, New Jersey, United States
$60k-$62k/yr OnsiteFull Time
FPGA design with Verilog/VHDL or high-level synthesis, IP integration, testbenches, and Xilinx boards; multi-clock domain designs; document designs.
Verilog, VHDL, SystemVerilog, C, High-Level Synthesis, Xilinx tools
3mo
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FPGA Engineer (NJ, Moorestown)
Moorestown, New Jersey, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Familiar with RTL, C/C++, Python, VHDL/Verilog, hardware security, FPGA design, and hardware-software integration; eligible for U.S. government security clearance; willingness to travel ~10%.
VHDL, Verilog, Vivado, GHDL, Questa, Quartus Prime, Zynq, Versal, Stratix, Agilex, AXI, ACE, Avalon, IP core, cocotb, pyuvm, Python, C, C++, Tcl
2mo
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ASIC/FPGA Verification Engineer III
Denver or Highlands Ranch or King of Prussia or Sunnyvale
$101k-$178k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering or equivalent, 3+ years professional ASIC/FPGA verification experience, SystemVerilog and UVM/OVM/VMM proficiency, HDL and scripting experience, ability to obtain/maintain DoD Secret clearance (US citizenship required).
SystemVerilog, Universal Verification Methodology (UVM), OVM, VMM, VHDL, Verilog, Linux, Perl, TCL, Python
2mo
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ASIC/FPGA Verification Engineer III
Denver or Highlands Ranch or King of Prussia or Sunnyvale
$101k-$201k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering (or equivalent), 3+ years ASIC/FPGA verification experience using UVM/OVM/VMM, HDL (VHDL/Verilog/SystemVerilog), ability to obtain DoD Secret clearance (US citizenship required); scripting (Perl/TCL/Python) and leadership experience preferred.
SystemVerilog, Universal Verification Methodology (UVM), OVM, VMM, VHDL, Verilog, Perl, TCL, Python, Linux
2mo
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ASIC/FPGA Design Engineer IV, TS/SCI Clearance
Boulder or King of Prussia or Littleton or Louisville or Sunnyvale
$124k-$246k/yr OnsiteFull Time
5+ YOEMust be US citizen with active Top Secret clearance, BS in Electrical Engineering or equivalent, 5+ years experience in ASIC/FPGA design/debug/verification, leadership and project management skills, and familiarity with project tools.
Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
1mo
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FPGA/Firmware Engineers in NY, NJ & PA
Liverpool or Owego or Syracuse or Moorestown or King of Prussia
$101k-$201k/yr OnsiteFull Time
5+ YOEBachelor's in STEM, 5+ years engineering experience, FPGA/ASIC/firmware experience, U.S. citizenship and ability to obtain/maintain Secret clearance, experience with VHDL/Verilog, C/C++, Python, FPGA tools and PCB tools.
C, C++, Assembly, Python, Perl, VHDL, Verilog, Altium, Cadence, Eagle, Vitis HLS, Vivado, Quartus, Git, SVN, PCIe, AXI, SPI
1mo
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Sr. FPGA Developer (Hybrid- Aberdeen Proving Ground, Maryland)
Aberdeen Proving Ground or Middletown
$150k-$175k/yr HybridFull Time
10+ YOEBachelor's in EE/CE, 10+ years FPGA design experience, strong Verilog/VHDL and Xilinx Vivado skills, RFSoC/Versal experience, RTL simulation and hardware debug experience, U.S. citizenship and Secret clearance (or ability to obtain).
Xilinx Vivado, Verilog, VHDL, Siemens Questa, Vivado Simulator, Integrated Logic Analyzer (ILA), VIO, JTAG, ADRV9009, AD9081, JESD204B/C, Ethernet, PCIe, Aurora, AXI-Lite, AXI-Stream, DMA, Tcl, Python
1mo
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SATCOM Systems Engineer (Hybrid- Aberdeen, Maryland)
Aberdeen Proving Ground or Wilmington or Middletown or United States
$135k-$165k/yr HybridFull Time
7+ YOEBachelor's in engineering, 7+ years DoD SATCOM systems experience, technical lead experience, proficiency producing systems engineering docs, hands-on experience with iDirect/Comtech/ViaSat modems, MIL-STD-188-164B/165B knowledge, basic Python and FPGA/DSP understanding, U.S. citizenship and active DoD Secret clearance.
MIL-STD-188-164B, MIL-STD-188-165B, iDirect, Comtech, ViaSat, Python, FPGA, DSP, spectrum analyzers, signal generators
3w
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Principal Firmware Engineer
Horsham, Pennsylvania, United States
$97k-$189k/yr HybridFull Time
8+ YOEBachelor's in EE or CS, 8+ years embedded/real-time firmware experience with microcontrollers and FPGA, expert C++ and object-oriented design, EM/CI-CD/DevOps experience, lab debugging skills, strong communication.
NIOS, ARM, GNU, C++, assembly, oscilloscope, logic analyzer, CI/CD, DevOps
2w
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Engineer II-Design
Allentown, Pennsylvania, United States
OnsiteFull Time
2+ YOE2+ years RTL design experience for ASIC, Bachelor’s in EE/CE/CS required, SystemVerilog and scripting (TCL/Perl/Python), Linux, static timing and simulation experience, US citizenship or permanent residency required.
SystemVerilog, Verilog, TCL, Perl, Python, LINUX, FPGA
1mo
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Technical Staff Engineer - Applications
San Jose or Addison or Allentown or Hauppauge
$91k-$232k/yr HybridFull Time
12+ YOEBachelors in EE/Comp Eng/Science required (Masters preferred); 12+ years FPGA architecture/design experience; 5+ years lab equipment use; expert VHDL/Verilog and C; experience with Libero/Vivado/Quartus, Linux, Keil/IAR/Eclipse, EDA tools; strong communication.
Libero, Vivado, Quartus, Keil, IAR, Eclipse, Linux, C, VHDL, Verilog, RISC-V, EDA tools, Oscilloscopes, Signal analyzers
1mo
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Advanced Embedded Engineer
Lansdale, Pennsylvania, United States
OnsiteFull Time
Experience with VHDL or Verilog, C/C++, serial protocols (UART, SPI, I²C, CAN), embedded debugging, RTOS, and ability to obtain security clearance; bachelor’s degree in EE/CE preferred.
VHDL, Verilog, C, C++, UART, SPI, I²C, CAN, FPGA, oscilloscope, logic analyzer, Real-time operating systems (RTOS)
1mo
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Cybersecurity Anti-Tamper Senior Engineer
Moorestown, New Jersey, United States
$91k-$172k/yr OnsiteFull Time
5+ YOEB.S. in Electrical/Computer/Systems Engineering, 5+ years related experience (or 3 with MS), ability to obtain DoD Secret clearance, experience with OS and programming languages, secure system/product design, integration/test, and strong communication skills.
C++, Linux, FPGA
3d
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Senior Specialist, Systems Engineering 1 (41936)
Bristol, Pennsylvania, United States
OnsiteFull Time
6+ YOEBachelor's +6 years (or Master's +4, or 10 years equivalent); ability to obtain Secret clearance; experience with digital electronics, FPGA/VHDL, requirements management, system integration, and technical leadership.
FPGA, VHDL, DOORS, JAMA, CPU, GPU
2mo
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Engineering Planner (Project Engineer)
Highlands Ranch or King of Prussia or Sunnyvale
$70k-$140k/yr OnsiteFull Time
US citizen able to obtain DoD Secret clearance. Experience or coursework in FPGA/ASIC design and HDL (VHDL, Verilog, SystemVerilog). Proficiency with Microsoft Project and JIRA. BS in EE preferred.
Microsoft Project, JIRA, VHDL, Verilog, SystemVerilog
2mo
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Principal Engineer – Network Evolution Architecture
Philadelphia, Pennsylvania, United States
HybridFull Time
10+ YOE Lead strategic architecture and system design for next-generation access and transport technologies; evaluate hardware/software architectures; design RF/optical networks; develop PoCs; collaborate with partners.
FPGA, ASIC, Python, RF, Optical networking, WiFi, O-RAN
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