18 fpga verification engineer jobs at 13 companies in Austin, TX
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Lead FPGA Design Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBachelor’s degree in a related technical field and 5–10 years of FPGA or platform engineering experience. Requires FPGA design, RTL, verification, timing, lab debugging, and digital interface expertise.
FPGA, RTL, AMD/Xilinx, Intel/Altera, SPI, I2C, UART, Ethernet, PCIe, JESD, digital oscilloscopes, logic analyzers, function generators, printed circuit boards (PCBs)
4w
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System FPGA Engineer
Santa Clara or Austin
$152k-$228k/yr OnsiteFull Time
5+ YOEBachelor's or higher in engineering/CS and 5+ years FPGA implementation and verification experience; proficiency in Verilog/SystemVerilog, Python, cocotb, git/GitHub, vendor FPGA toolchains; strong communication skills.
Python, git, GitHub, cocotb, Verilog, SystemVerilog, AMD/Xilinx Vivado/Vitis, Intel/Altera Quartus Prime, JTAG, oscilloscope
1mo
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
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FPGA Design Engineer III
Austin, Texas, United States
OnsiteFull Time
3+ YOE3+ years Verilog RTL FPGA design experience, Bachelor's degree in EE/CE, full FPGA design flow knowledge, proficiency with major FPGA tool suites, and experience with verification and timing closure.
Verilog, VHDL, SystemVerilog, Microchip PolarFire SoC, RISC-V, PCIe, Ethernet, SERDES, UVM, Libero SoC, Xilinx Vivado, Intel Quartus, logic analyzers, oscilloscopes, Linux
1mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
2mo
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Principal Design Verification Engineer (Silicon Engineering)
Irvine or Austin or Redmond or Sunnyvale
$210k-$300k/yr OnsiteFull Time
10+ YOEBachelor in ECE/CS and 10+ years in design verification; strong UVM/OVM/VMM, Python, and RTL/ASIC/FPGA experience.
UVM, OVM, VMM, Python, RTL, ASIC, FPGA, constrained random verification
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Senior Firmware Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBS/MS in EE or Computer Engineering required; 5+ years firmware verification experience in pre-silicon; SystemVerilog, C, Python/Perl skills; familiarity with RTL, emulation, and lab test equipment.
SystemVerilog, UVM, C, Python, Perl, RTL, FPGA, QEMU, SimVision, Verdi, oscilloscopes, power supplies, logic analyzers
2mo
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Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
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Principal Silicon Design Verification Engineer
Mountain View or Austin or Redmond or Raleigh or Hillsboro
$143k-$275k/yr HybridFull Time
3+ YOEDegree in EE/CE/CS (or equivalent) with multi-year technical experience depending on degree; expertise in C/C++, SystemVerilog, UVM, pre-silicon verification, scripting (Python/Ruby/Perl), FPGA/emulation, build flows, and hardware debug; must pass Microsoft Cloud Background Check and meet export-control citizenship/residency requirements.
C, C++, SystemVerilog, UVM, Python, Ruby, Perl, HAPS, Xilinx, Makefiles, linker scripts, assembly, AMBA (AXI/AHB/APB), JTAG, SPI, I2C/I3C, USB, logic analyzers, oscilloscopes, multimeters, FPGA, emulation
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Principal Design Verification Engineer
Mountain View or Redmond or Hillsboro or Austin or Raleigh
$143k-$275k/yr HybridFull Time
8+ YOEAdvanced degree or equivalent experience in EE/CE/CS with 3–8+ years technical experience; strong verification, testbench, simulation, and debug skills; ability to pass Microsoft security and export-control screenings.
Verilog, VHDL, C, C++, Python, Ruby, Perl, SystemVerilog, UVM, FPGA
4w
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Design Verification Engineer – Physical AI Compute
Santa Clara or Austin or Boston
$75k-$275k/yr OnsiteFull Time
Experience verifying complex digital/SoC systems with SystemVerilog/UVM, C/C++, assertions, formal, emulation and debugging across HW/SW boundaries.
SystemVerilog, UVM, C, C++, formal verification, emulation, FPGA
1mo
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
4d
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Manager / Senior Manager – Design Verification
Hyderabad or Austin
OnsiteFull Time
10+ YOERequires a B.E./B.Tech or M.E./M.Tech in engineering or VLSI, 10–15 years of design verification experience, and expertise in SystemVerilog, UVM, assertions, coverage, regression, leadership, and cross-functional delivery.
SystemVerilog, UVM, Python, Perl, Tcl, UPF, FPGA
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Senior ASIC Design Engineer - Terawave
San Diego or California or Austin or Kent or Texas or Washington
$230k-$323k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in Electrical Engineering (or related), 8+ years experience in pre- and post-silicon SoC verification, strong SystemVerilog and DSP knowledge, emulation/FPGA/silicon bring-up experience, and verification methodology expertise.
SystemVerilog, MATLAB, SystemC, C, FPGA
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Senior Principal Hardware Design Engineer
Austin, Texas, United States
$133k-$226k/yr HybridFull Time
10+ YOEBS in EE +12y or MS in EE +10y; high-speed digital circuit design, FPGA and microprocessor schematic/layout, PCIe, signal integrity, MATLAB, HyperLynx, Mentor/Siemens Xpedition, test & verification, leadership and strong communication.
MATLAB, HyperLynx, Mentor/Siemens Xpedition, PCIe, FPGA, DDR3, DDR4, Ethernet, 1553, SERDES, Fiber Optic
2mo
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Design Engineer I - Modem Design
Austin, Texas, United States
$79k-$146k/yr HybridFull Time
Degree in electrical/computer engineering or related; experience with RTL design using Verilog/SystemVerilog, digital design and verification, MATLAB/Python for automation, and familiarity with FPGA/ASIC flows and wireless/DSP concepts.
Verilog, SystemVerilog, MATLAB, Python, Questa
2mo
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Design Engineer I - Modem Design
Austin, Texas, United States
$79k-$146k/yr HybridFull Time
Bachelor's in EE/CE (or related); experience with RTL design using Verilog/SystemVerilog, digital design verification, and basic Python or MATLAB skills; familiarity with FPGA/SoC bring-up and wireless DSP is a plus.
Verilog, SystemVerilog, Python, MATLAB, Questa
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Field Application Engineer – PowerPro
Austin or Costa Mesa or San Diego or Santa Clara
$147k-$293k/yr HybridFull Time
3+ YOE3+ years RTL (ASIC/FPGA) design experience, strong Verilog/SystemVerilog/VHDL skills, knowledge of STA/synthesis/verification, RTL power analysis experience, scripting (Tcl, Python), BS/MS in EE/CS or related, strong communication.
Verilog, SystemVerilog, VHDL, Tcl, Python, PrimePower, PowerArtist, UPF, CPF
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