4 git jobs at 3 companies in Rensselaer, IN
2mo
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Principal Software Engineer, Android
Milwaukee, Wisconsin, United States
$112k-$154k/yr OnsiteFull Time
5+ YOE5+ years software engineering, 2+ years Android, Bachelor's/Master’s in CS, Java/Kotlin, Android SDK/NDK, CI/CD, Agile, regulatory familiarity.
Java, Kotlin, JavaScript, TypeScript, C++, Android SDK, NDK, Android Studio, Azure DevOps, Jira, Git, SVN, CI/CD
1mo
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Principal Engineer - FPGA/ASIC Design
Indianapolis or West Lafayette
$113k-$184k/yr HybridFull Time
3+ YOEU.S. citizen with degree in electronics/computer engineering and 3+ years experience (or higher degree), expertise in FPGA/ASIC design (VHDL/Verilog/SystemVerilog), DO-254 verification, timing closure, synthesis, testbenches, lab validation, and scripting (TCL/Python/Shell).
VHDL, Verilog, SystemVerilog, DO-254, TCL, Python, Shell, Windows, Linux, Git, SVN, Actel, Xilinx, MATLAB, Simulink, Cameo Systems Modeler (MagicDraw), ILA, JTAG, oscilloscopes, logic analyzers
2mo
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Co-op - Firmware Engineering (Lafayette, IN, US)
Lafayette, Indiana, United States
OnsiteInternship
0+ YOECo-op required; undergrad in Computer, Electrical, or Software Engineering; on-site Lafayette, IN; 3-semester rotation starting Aug 2026; Masters not considered; paid position; housing not provided.
GitLab, CI/CD, Embedded Firmware, Unit Testing, Static Analysis, Regression Testing
2w
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Principal Engineer - FPGA/ASIC Design
Indianapolis or West Lafayette
$113k-$184k/yr HybridFull Time
3+ YOEDesign, verify, integrate and test FPGA/ASIC solutions; develop RTL (VHDL/Verilog/SystemVerilog); achieve timing closure; lab validation; scripting and version control experience; U.S. citizenship required.
VHDL, Verilog, SystemVerilog, ILA, JTAG, TCL, Python, Shell, Git, SVN, Actel, Xilinx, MATLAB, Simulink, Cameo Systems Modeler (MagicDraw), Windows, Linux