3mo
Save
Mark Applied
Hide
Formal Verification Engineer
Austin or Beaverton or Cupertino
OnsiteFull Time
3+ YOEBachelor's degree and at least 3 years of silicon verification or related experience; strong knowledge of formal verification methods and hardware design.
VLSI, Digital Logic, Formal Verification, SVA, PSL, EDA Tools, Scripting, Python
3mo
Save
Mark Applied
Hide
Formal Verification Engineer
Austin or Beaverton or Cupertino
HybridFull Time
10+ YOEBS degree with 10+ years in silicon validation or related field; strong formal verification experience and knowledge of hardware, software, and SoC design.
SVA, PSL, EDA tools, Python, Shell, Perl
3mo
Save
Mark Applied
Hide
Hardware Design Engineer
Hillsboro, Oregon, United States
$107k-$199k/yr HybridFull Time
5+ YOEStrong SystemVerilog/Verilog RTL design, ASIC/FPGA experience, RTL verification, scripting, 5+ years, BSEE.
SystemVerilog, Verilog, Questa, Incisive, VCS, Python, Perl, Tcl
1mo
Save
Mark Applied
Hide
Senior CPU Design Verification Engineer, Emulation
Austin or Mountain View or Portland or Poughkeepsie
$163k-$237k/yr OnsiteFull Time
8+ YOE8+ years in design verification (UVM/SystemVerilog) and hardware emulation; reproducing post-silicon failures; experience with Synopsys Verdi/Cadence SimVision and scripting (Python, TCL, Bash).
UVM, SystemVerilog, Synopsys Verdi, Cadence SimVision, Python, TCL, Bash, JTAG
4w
Save
Mark Applied
Hide
Principal Silicon Design Verification Engineer
Mountain View or Austin or Redmond or Raleigh or Hillsboro
$143k-$275k/yr HybridFull Time
3+ YOEDegree in EE/CE/CS (or equivalent) with multi-year technical experience depending on degree; expertise in C/C++, SystemVerilog, UVM, pre-silicon verification, scripting (Python/Ruby/Perl), FPGA/emulation, build flows, and hardware debug; must pass Microsoft Cloud Background Check and meet export-control citizenship/residency requirements.
C, C++, SystemVerilog, UVM, Python, Ruby, Perl, HAPS, Xilinx, Makefiles, linker scripts, assembly, AMBA (AXI/AHB/APB), JTAG, SPI, I2C/I3C, USB, logic analyzers, oscilloscopes, multimeters, FPGA, emulation
2mo
Save
Mark Applied
Hide
Validation / Verification Eng, Sr Manager-17415
Hillsboro, Oregon, United States
$166k-$249k/yr OnsiteFull Time
Lead and manage a mixed hardware team; oversee high-speed SerDes validation, debugging, and lab operations.
Oscilloscopes, Network analyzers, High-speed probing tools, MATLAB, Python, Verilog