8 hardware verification engineer jobs at 5 companies in Gustine, CA

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Verification Engineer
San Jose, California, United States
OnsiteFull Time
Lumilens
Lumilens: Designs photonic interconnects for AI supercomputing infrastructure.
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
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Verification Lead (Lead DV)
San Jose, California, United States
OnsiteFull Time
Lumilens
Lumilens: Designs photonic interconnects for AI supercomputing infrastructure.
10+ YOE10+ years ASIC/SoC verification experience with team leadership; deep UVM/SystemVerilog, hardware-assisted verification (emulation/FPGA), mixed-signal verification, and regression/CI at scale.
UVM, SystemVerilog, Palladium, Veloce, HAPS, Protium, Verilog-AMS, UPF, UCIe, PCIe, CXL, Ethernet, Reed-Solomon, FPGA
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Senior ASIC Verification Engineer
San Jose, California, United States
RemoteFull Time
Cornelis Networks
Cornelis Networks: High-performance networking solutions for AI and HPC datacenters.
8+ YOE8+ years in networking hardware verification; UVM/SystemVerilog; RTL debugging; complex SoCs; Git/SVN; BS in CE/CS/EE.
UVM, SystemVerilog, VCS, Verdi, Git, SVN, Python, TCL, Perl, Shell, TCP/IP, RDMA, RoCE, IPSec
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FPGA Engineer (CA, San Jose)
San Jose, California, United States
HybridFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience in FPGA design and verification, proficiency in RTL/C/C++, Python; familiarity with VHDL/Verilog, hardware security, IP core development, and FPGA tools.
C, C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Xilinx, Altera, Versal, Stratix, Avalon, AXI, ACE, IP cores, cocotb, pyuvm
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Sr. Aircraft Software Integration Engineer
San Jose or Salinas
$144k-$180k/yr OnsiteFull Time
Archer
ArcherNYSE: ACHR: Develops electric vertical takeoff and landing aircraft for urban mobility.
6+ YOE6+ years with real-time embedded systems, BS in relevant engineering, experience with flight controls/avionics, systems integration and verification, lab hardware/software integration, C, MATLAB/Simulink, bash/Python, and familiarity with communication protocols.
C, MATLAB/Simulink, bash, Python, RS-422/485, CAN, ARINC-429, AFDX, Ethernet, TCP/IP, System Load Manager (SLM), oscilloscope, bus analyzer, FPGAs, VHDL, Verilog, RTOS
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Senior QA Engineer – Performance & Reliability
San Jose, California, United States
$100k-$160k/yr OnsiteFull Time
Axiado
Axiado: Creates AI-driven security processors for data center infrastructure.
5+ YOE5+ years embedded system testing; performance verification; reliability engineering; Linux/Unix; Python; CI/CD; hardware/firmware knowledge.
Python, C/C++, Linux, Jenkins, GitLab CI, Git, SPEC, IOzone, iperf
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Sr. Embedded Software Engineer
San Jose, California, United States
$140k-$170k/yr OnsiteFull Time
Archer
ArcherNYSE: ACHR: Develops electric vertical takeoff and landing aircraft for urban mobility.
3+ YOE3+ years experience, BS in EE/CE/CS or related, strong C/C++ and Python, experience with DO-178C/ISO 26262 safety standards, full software verification lifecycle, low-level protocol testing, RTOS and hardware debugging skills.
DO-178C, ISO 26262, ASIL, C/C++, Python, Software-in-the-Loop (SIL), Hardware-in-the-Loop (HIL), CAN, RS-422/485, ARINC-429, SPI, I2C, Ethernet, RTOS, oscilloscopes, logic analyzers, power supplies
2mo
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ASIC DFT Technical Lead
San Jose, California, United States
$211k-$351k/yr HybridFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
10+ YOE10+ years in ASIC hardware development; RTL/verification; DFT/DFx; JTAG; BIST; post-silicon test; RTL QA.
JTAG, BIST, RTL, lint, CDC, Python, Tcl, Perl