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Principal Design Verification Engineer – CPU Core Hardware Prefetch
Austin or Santa Clara
OnsiteFull Time
12+ YOE12+ years CPU/SoC functional verification experience, BS/MS/PhD in EE/CE/CS, deep CPU microarchitecture and hardware prefetch verification expertise, strong debug and scripting skills, technical leadership and mentoring experience.
3mo
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Formal Verification Engineer
Austin or Beaverton or Cupertino
OnsiteFull Time
3+ YOEBachelor's degree and at least 3 years of silicon verification or related experience; strong knowledge of formal verification methods and hardware design.
VLSI, Digital Logic, Formal Verification, SVA, PSL, EDA Tools, Scripting, Python
2mo
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Member of Technical Staff, Hardware, Design Verification Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOE5+ years industry experience, BS in EE/CE/CS, deep SystemVerilog and UVM experience, verification methodology expertise, familiarity with emulation/prototyping and formal methods, strong collaboration and debugging skills.
SystemVerilog, UVM, ZeBu, HAPS, Palladium, Protium, Python, Perl, Bash, TCL, SVA, Jasper, VC Formal, AXI, CHI
3mo
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GPU Design Verification Engineer
San Diego or Santa Clara or Boxborough or Austin
$162k-$273k/yr OnsiteFull Time
2+ YOEBachelor's +4 yrs (or Master's +3 / PhD +2) in Comp Eng/CS/EE; experience in hardware/software/systems engineering; verification skills with System Verilog/UVM, Verilog/VHDL, C/C++; scripting and emulation exposure preferred.
System Verilog, UVM, Verilog, VHDL, C/C++, Python, Make, Airflow, Veloce, Palladium, Zebu, FPGA, Protium, HAPS, qemu, GNU Toolchain, Visual Studio, gdb, uboot, uefi, Vulkan, DX11, DX12, Windows, Linux
3w
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Senior ASIC Verification Engineer
Austin or Santa Clara
$136k-$265k/yr HybridFull Time
5+ YOEBachelors/Masters in CS/CE/EE (or equivalent experience), 5+ years experience, SystemVerilog OOP, verification methodology (UVM), VCS/Debussy/GDB exposure, experience with random stimulus, functional coverage, assertions, firmware/hardware verification.
SystemVerilog, VCS, Debussy, GDB, UVM, C, RISC-V Assembly
3mo
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Design Verification Engineer - Formal
Austin, Texas, United States
$127k-$217k/yr OnsiteFull Time
Strong programming/scripting; hands-on formal verification tools; knowledge of hardware design; collaborative; eager to learn.
Formal verification tools, EDA tools, Programming and scripting languages
1mo
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Senior Hardware Test Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years hardware design verification experience; Bachelor’s in Mechanical/Electrical/Mechatronics (Master's preferred); proficiency with lab test equipment, DAQ, Python/C++/MATLAB, CAD (SolidWorks or NX), and requirements tools.
oscilloscopes, multimeters, thermal chambers, vibration tables, National Instruments, LabVIEW, Beckhoff, DAQ, dynamometers, load cells, Python, C++, MATLAB, SolidWorks, NX, Jama, Polarion, JIRA, BLDC motors
2mo
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Hardware Engineer - ML Acceleration, Annapurna Labs
Austin or Cupertino
OnsiteFull Time
Bachelor's in Electrical Engineering; strong debugging; multi-level verification experience.
ARM, DSP ISA, Python, Perl, Formal verification tools
1mo
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Senior CPU Design Verification Engineer, Emulation
Austin or Mountain View or Portland or Poughkeepsie
$163k-$237k/yr OnsiteFull Time
8+ YOE8+ years in design verification (UVM/SystemVerilog) and hardware emulation; reproducing post-silicon failures; experience with Synopsys Verdi/Cadence SimVision and scripting (Python, TCL, Bash).
UVM, SystemVerilog, Synopsys Verdi, Cadence SimVision, Python, TCL, Bash, JTAG
1mo
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Principal Silicon Design Verification Engineer
Mountain View or Austin or Redmond or Raleigh or Hillsboro
$143k-$275k/yr HybridFull Time
3+ YOEDegree in EE/CE/CS (or equivalent) with multi-year technical experience depending on degree; expertise in C/C++, SystemVerilog, UVM, pre-silicon verification, scripting (Python/Ruby/Perl), FPGA/emulation, build flows, and hardware debug; must pass Microsoft Cloud Background Check and meet export-control citizenship/residency requirements.
C, C++, SystemVerilog, UVM, Python, Ruby, Perl, HAPS, Xilinx, Makefiles, linker scripts, assembly, AMBA (AXI/AHB/APB), JTAG, SPI, I2C/I3C, USB, logic analyzers, oscilloscopes, multimeters, FPGA, emulation
3w
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Senior Principal Hardware Design Engineer
Austin, Texas, United States
$133k-$226k/yr HybridFull Time
10+ YOEBS in EE +12y or MS in EE +10y; high-speed digital circuit design, FPGA and microprocessor schematic/layout, PCIe, signal integrity, MATLAB, HyperLynx, Mentor/Siemens Xpedition, test & verification, leadership and strong communication.
MATLAB, HyperLynx, Mentor/Siemens Xpedition, PCIe, FPGA, DDR3, DDR4, Ethernet, 1553, SERDES, Fiber Optic
3mo
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Systems Architecture, Integration, and Test Engineer (Test & Verification)
Austin, Texas, United States
OnsiteFull Time
2+ YOE2+ years in design/verification/test engineering; bachelor’s or higher in engineering; experience with hardware systems and test campaigns; travel as needed.
Jama, DOORS, Innoslate, 3DX, Cameo, Flow, Palantir Foundry, Confluence, Excel
1mo
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ASIC Design Engineer - Hardware
Austin, Texas, United States
$116k-$219k/yr HybridFull Time
2+ YOEBS in EE/CE (or equivalent), 2+ years industry experience, strong Perl/Python scripting, RTL design (Verilog), SystemVerilog verification, SOC design/implementation and automation experience, CDC/performance debugging skills.
Perl, Python, Verilog, SystemVerilog, dc_shell, VCS, Debussy, GDB
2mo
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Applications Engineering, Sr Staff Engineer-17205
Austin, Texas, United States
$136k-$204k/yr OnsiteFull Time
8+ YOEBachelor’s degree in engineering plus 8+ years in FPGA prototyping or hardware verification; strong HW/SW validation and debugging experience.
FPGA, HAPS, HDL, Hardware verification, Software bring-up
6d
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Manager, Spacecraft Mission Testbed Development
Austin, Texas, United States
OnsiteFull Time
8+ YOE3+ MgmtBachelor's in engineering, 8+ years spacecraft/aerospace hardware experience, 3+ years technical leadership, HITL/EGSE testbed expertise, systems integration and verification experience, strong communication, occasional travel, US authorization per ITAR.
Hardware-in-the-Loop (HITL), EGSE
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