2w
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Principal Design Verification Engineer – CPU Core Hardware Prefetch
Austin or Santa Clara
OnsiteFull Time
12+ YOE12+ years CPU/SoC functional verification experience, BS/MS/PhD in EE/CE/CS, deep CPU microarchitecture and hardware prefetch verification expertise, strong debug and scripting skills, technical leadership and mentoring experience.
1mo
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Senior ASIC Verification Engineer
Austin or Santa Clara
$136k-$265k/yr HybridFull Time
5+ YOEBachelors/Masters in CS/CE/EE (or equivalent experience), 5+ years experience, SystemVerilog OOP, verification methodology (UVM), VCS/Debussy/GDB exposure, experience with random stimulus, functional coverage, assertions, firmware/hardware verification.
SystemVerilog, VCS, Debussy, GDB, UVM, C, RISC-V Assembly
2mo
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Member of Technical Staff, Hardware, Design Verification Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOE5+ years industry experience, BS in EE/CE/CS, deep SystemVerilog and UVM experience, verification methodology expertise, familiarity with emulation/prototyping and formal methods, strong collaboration and debugging skills.
SystemVerilog, UVM, ZeBu, HAPS, Palladium, Protium, Python, Perl, Bash, TCL, SVA, Jasper, VC Formal, AXI, CHI
5d
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ASIC SoC Verification Engineer (788438)
Austin, Texas, United States
HybridFull Time
Experience in SoC/IP/SubSystem verification, SystemC/TLM and RTL environments, hardware emulation, knowledge of high-speed interfaces, strong problem-solving and communication;BS required, MS preferred.
SystemC/TLM, RTL, hardware emulation
5d
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ASIC SoC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Experience in SoC/IP/Subsystem verification, SystemC/TLM and RTL verification, hardware emulation familiarity, strong problem-solving and communication; BS required (MS preferred).
SystemC, TLM, RTL, hardware emulation
1mo
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Senior Hardware Test Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years hardware design verification experience; Bachelor’s in Mechanical/Electrical/Mechatronics (Master's preferred); proficiency with lab test equipment, DAQ, Python/C++/MATLAB, CAD (SolidWorks or NX), and requirements tools.
oscilloscopes, multimeters, thermal chambers, vibration tables, National Instruments, LabVIEW, Beckhoff, DAQ, dynamometers, load cells, Python, C++, MATLAB, SolidWorks, NX, Jama, Polarion, JIRA, BLDC motors
5d
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$114k-$172k/yr OnsiteFull Time
2+ YOEBachelor's in CS/CE or equivalent,2+ years SystemVerilog/UVM or C/C++ hardware verification, experience with EDA simulation tools and scripting (Python,TCL,Perl,Shell),and RTL debug/root-cause analysis.
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, EDA simulation tools, Emulation
1mo
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ASIC Verification Engineer - New College Grad 2026
Austin or Santa Clara
$100k-$190k/yr OnsiteFull Time
Pursuing or recently completed a BS/MS/PhD in EE, Computer Engineering, or CS; knowledgeable in verification methodology (UVM, assertions, coverage), SystemVerilog OOP, simulation/debug tools, firmware/hardware interactions, and strong debugging skills.
SystemVerilog, VCS, Debussy, GDB, UVM, C, RISCV
1mo
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Principal Silicon Design Verification Engineer
Mountain View or Austin or Redmond or Raleigh or Hillsboro
$143k-$275k/yr HybridFull Time
3+ YOEDegree in EE/CE/CS (or equivalent) with multi-year technical experience depending on degree; expertise in C/C++, SystemVerilog, UVM, pre-silicon verification, scripting (Python/Ruby/Perl), FPGA/emulation, build flows, and hardware debug; must pass Microsoft Cloud Background Check and meet export-control citizenship/residency requirements.
C, C++, SystemVerilog, UVM, Python, Ruby, Perl, HAPS, Xilinx, Makefiles, linker scripts, assembly, AMBA (AXI/AHB/APB), JTAG, SPI, I2C/I3C, USB, logic analyzers, oscilloscopes, multimeters, FPGA, emulation
1mo
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Sr. Hardware Engineer - ML Acceleration, Annapurna Labs
Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
7+ YOE7+ years ASIC, digital and analog/RF design, verification and physical design experience; experience with UVM, C/SystemC, MATLAB/Python/C++; emulation, post-silicon validation, and SOC bring-up experience; BS in EE required.
UVM, C, System C, MATLAB, Python, C++, Pearl, Git, CI/CD, SPI, I2C, I3C, UART
1mo
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Senior Principal Hardware Design Engineer
Austin, Texas, United States
$133k-$226k/yr HybridFull Time
10+ YOEBS in EE +12y or MS in EE +10y; high-speed digital circuit design, FPGA and microprocessor schematic/layout, PCIe, signal integrity, MATLAB, HyperLynx, Mentor/Siemens Xpedition, test & verification, leadership and strong communication.
MATLAB, HyperLynx, Mentor/Siemens Xpedition, PCIe, FPGA, DDR3, DDR4, Ethernet, 1553, SERDES, Fiber Optic
6d
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Sr. Engineer, Silicon Validation , Annapurna Labs
Cupertino or Austin
$159k-$248k/yr OnsiteFull Time
6+ YOE6+ years verification/chip design experience, 2+ years HW/SW co-design testing, experience with ML accelerator SOC validation, emulation platforms, and hardware verification methodologies.