8 hardware verification engineer jobs at 6 companies in Newman, CA
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Verification Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
3w
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
1mo
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Verification Lead (Lead DV)
San Jose, California, United States
OnsiteFull Time
10+ YOE10+ years ASIC/SoC verification experience with team leadership; deep UVM/SystemVerilog, hardware-assisted verification (emulation/FPGA), mixed-signal verification, and regression/CI at scale.
UVM, SystemVerilog, Palladium, Veloce, HAPS, Protium, Verilog-AMS, UPF, UCIe, PCIe, CXL, Ethernet, Reed-Solomon, FPGA
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AI/ML Silicon Verification Solutions Engineer – Tools
San Jose, California, United States
HybridFull Time
Experience applying AI/ML to hardware verification, strong programming and verification background, familiarity with SystemVerilog/UVM, cloud and CI/CD deployment, and BS/MS in EE/CS/CE.
Python, C, C++, Perl, SystemVerilog, UVM, AWS, GCP, Azure, OCI, CI/CD, Jenkins, GitHub Actions, Git, Perforce, Model Context Protocol (MCP), LLM
2mo
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Senior ASIC Verification Engineer
San Jose, California, United States
RemoteFull Time
8+ YOE8+ years in networking hardware verification; UVM/SystemVerilog; RTL debugging; complex SoCs; Git/SVN; BS in CE/CS/EE.
UVM, SystemVerilog, VCS, Verdi, Git, SVN, Python, TCL, Perl, Shell, TCP/IP, RDMA, RoCE, IPSec
3mo
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FPGA Engineer (CA, San Jose)
San Jose, California, United States
HybridFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience in FPGA design and verification, proficiency in RTL/C/C++, Python; familiarity with VHDL/Verilog, hardware security, IP core development, and FPGA tools.
C, C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Xilinx, Altera, Versal, Stratix, Avalon, AXI, ACE, IP cores, cocotb, pyuvm
1mo
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Sr. Embedded Software Engineer
San Jose, California, United States
$140k-$170k/yr OnsiteFull Time
3+ YOE3+ years experience, BS in EE/CE/CS or related, strong C/C++ and Python, experience with DO-178C/ISO 26262 safety standards, full software verification lifecycle, low-level protocol testing, RTOS and hardware debugging skills.
DO-178C, ISO 26262, ASIL, C/C++, Python, Software-in-the-Loop (SIL), Hardware-in-the-Loop (HIL), CAN, RS-422/485, ARINC-429, SPI, I2C, Ethernet, RTOS, oscilloscopes, logic analyzers, power supplies
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Senior/Principal R&D Digital Systems Security, Hybrid
Albuquerque or Livermore
$140k-$281k/yr HybridFull Time
5+ YOEBachelor's plus 5 years relevant experience (or equivalent), ability to obtain DOE Q-level clearance, expertise in hardware/software security, formal methods, and familiarity with secure-system design and verification.
RocQ, Lean, C, C++, Java, Python, Rust, Assembly, ASIC, FPGA, NIST, CNSS