12 interconnection engineer jobs at 7 companies in Keizer, OR
1mo
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Senior Manager / Director, Load Interconnection & Grid Integration
Portland or North America
HybridFull Time
10+ YOEBachelor's in Electrical Engineering, 10+ years transmission planning/load interconnection experience, ISO/RTO expertise, EMT modeling and transmission study experience, PSCAD/PSS®E/PSLF/EMTP-RV/PowerFactory/ETAP familiarity, PE preferred.
PSCAD, PSS®E, PSLF, EMTP-RV, PowerFactory, ETAP
3mo
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Silicon Packaging Design Engineer
Phoenix or Hillsboro
$106k-$200k/yr OnsiteFull Time
3+ YOEBachelor's degree with 3+ years or Master's with 2+ years in Electrical/Computer Engineering or STEM; experience with custom layout/EDA tools; silicon physical layout and interconnects; strong collaboration.
Virtuoso, Innovus, FusionCompiler, ICvalidator, Calibre
1w
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Senior Power Systems Engineer, Resource Integration
Dallas or Oak Brook or Medford or Portland or Houston or Seattle or Austin or New York City or Oakland or San Diego
$120k-$175k/yr HybridFull Time
5+ YOEBachelor’s degree in electrical or mechanical engineering, 5+ years of relevant experience, power-system modeling expertise, North American grid interconnection knowledge, English communication skills, travel availability, and a valid driver’s license.
PSS/E, TARA, PSLF, PowerWorld, PSCAD, Python, TSAT, ASPEN, CYME, ETAP, Synergi Electric, DIgSILENT, EMTP-RV, AutoCAD, Autodesk, Talkspace
1w
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Back End( BE) Process Integration Engineer
Hillsboro, Oregon, United States
$104k-$171k/yr OnsiteFull Time
PhD in a related semiconductor field and hands-on cleanroom experience in process development, interconnect integration, characterization, or fab operations; analytical, experimental design, and communication skills required.
JMP, Python, SQL, MATLAB, JSL, TCL, Statistical Process Control (SPC), Design of Experiments (DOE), Failure Mode and Effects Analysis (FMEA), Cpk, Ppk, Control charts, Capability analysis, KLA, Applied Materials
1mo
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Senior Fabric Design Verification Engineer
Hillsboro or Redmond or Austin or Raleigh
$120k-$235k/yr HybridFull Time
1+ YOEExperience verifying fabric/interconnect or IP using UVM/System Verilog, Python scripting, and applying coverage-based/random-stimulus techniques; ability to pass security/export screening and provide proof of citizenship or residency.
Universal Verification Methodology (UVM), System Verilog, Python
1w
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Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
Santa Clara or Hillsboro
$136k-$265k/yr OnsiteFull Time
5+ YOEMaster’s degree in electrical engineering, computer engineering, or computer science, or equivalent experience; 5+ years in high-performance semiconductor design; synthesis, timing analysis, floor-planning, and physical design tools expertise.
Verilog, RTL, DFT, ECO
1w
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Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
Santa Clara or Hillsboro
$136k-$265k/yr OnsiteFull Time
5+ YOEMaster’s degree in electrical engineering, computer engineering, computer science, or equivalent; 5+ years in high-performance semiconductor design; synthesis, timing analysis, floor-planning, physical design tools, and ASIC design flow expertise.
Verilog, RTL, DFT, ECO
3d
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Silicon Photonics EPM, Data Center SoC
Beaverton, Oregon, United States
OnsiteFull Time
Seeking an engineering leader with curiosity about optics, photonics, silicon interconnects, and next-generation data center system-on-chip technology.
Silicon Photonics, optical I/O
3w
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Server CPU SoC Architect
Hillsboro or Beaver Brook or Santa Clara or Austin or Phoenix
$142k-$269k/yr HybridFull Time
4+ YOEBachelor's in related field with 4+ years (or Master's/PhD with less), 4+ years CPU/SoC architecture experience, expertise in performance and power modeling, ISA and interconnect knowledge.
3w
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Datacenter Compute Accelerator Architect
San Jose or San Diego or Portland or Austin
$211k-$356k/yr OnsiteFull Time
8+ YOEBachelor’s degree in EE/CE/CS, 8+ years in CPU/SoC/accelerator architecture, expertise in hardware acceleration, interconnects, virtualization, proficiency in C/C++ and Python, gem5 experience preferred.
gem5, C, C++, Python
2mo
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Senior SoC Chiplet Architect
Santa Clara or Fort Collins or Hillsboro or Folsom or Austin or Phoenix
$164k-$269k/yr HybridFull Time
7+ YOEBachelor's in EE/CE/STEM and 7+ years SoC/system architecture experience with multi-die/chiplet partitioning, D2D interconnects, trade-off studies, and cross-functional technical leadership.
3w
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Datacenter Compute SoC Architect
San Jose or San Diego or Portland or Austin
$211k-$356k/yr OnsiteFull Time
10+ YOE10+ years SoC/compute architecture experience, 3+ years in datacenter/server SoCs; Bachelor’s degree in EE/CE/CS; expertise in CPU/memory/Interconnect, PCIe/CXL, and performance modeling.
C++, SystemC, UCIe, PCIe, CXL, ARM AMBA CHI, AXI