3mo
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Staff Foundry Interface Design Engineer- HBM - TPG
Folsom, California, United States
$175k-$297k/yr OnsiteFull Time
4+ YOEBachelor's in EE (4+ yrs industry experience), hands-on foundry PDK experience at advanced CMOS nodes, EDA tools, CMOS circuit design, parasitic extraction, circuit simulation, FinFET/GAA knowledge; Python and reliability modeling preferred.
PDKs, EDA tools, Python
3mo
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Staff Foundry Interface Design Engineer- HBM - TPG
Folsom, California, United States
$162k-$344k/yr HybridFull Time
4+ YOEBSEE or higher with 4+ years of experience; experience with Foundry PDKs (FinFET/GAA), EDA tools, CMOS design; Python scripting; able to collaborate across teams.
PDKs, EDA tools, Python, CMOS design, FinFET, GAA
2mo
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Design Verification Engineer
Minneapolis or Boise or Folsom or Richardson or San Jose
$178k-$389k/yr OnsiteFull Time
6+ YOEBachelor's in Electrical or Computer Engineering; 6–12 years DV experience using UVM/SystemVerilog; builds DV environments; strong coverage and debugging skills; experience with I2C/SPI/APB/AHB interfaces.
UVM, SystemVerilog, JasperGold, VC Formal, PRBS, eye monitor
2d
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Systems Engineer V -Strategic Systems, Systems Engineer MSAD
Folsom, California, United States
$153k-$197k/yr OnsiteFull Time
10+ YOEU.S. citizen with ability to obtain DoD Secret clearance; 10+ years modeling and controls experience in aerospace/propulsion; bachelor\u0002s in STEM; mastery of control theory, propulsion modeling, and customer interfacing.
MATLAB/Simulink, Python, SysML
1mo
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Staff Mixed-Signal Design Engineer, Pathfinding
Folsom or Boise or San Jose
$116k-$246k/yr OnsiteFull Time
7+ YOE7+ years in custom mixed-signal circuit design; UNIX and CADENCE; memory interface knowledge.
UNIX, Cadence Design System, HSPICE, Finesim, SPF extraction
1mo
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HBM SIPI, Staff Engineer
Richardson or Folsom
$146k-$297k/yr OnsiteFull Time
5+ YOE5+ years SI/PI modeling and analysis experience; deep SI/PI and electromagnetic knowledge; experience with Keysight ADS and Synopsys HSPICE; PDN and high-speed interface experience preferred.
Keysight ADS, Synopsys HSPICE, ANSYS HFSS, SIwave, Cadence PowerSI, Cadence PowerDC, SPICE
2mo
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SMTS Design Verification Engineer
Minneapolis or Boise or Folsom or Richardson or San Jose
$178k-$389k/yr OnsiteFull Time
6+ YOEBS/MS/PhD in EE/CE or related; 6+ years UVM/SystemVerilog functional verification; experience building UVM testbenches, coverage-driven methodology, protocol/interface verification, RTL/testbench debug, and post-silicon bring-up support.
UVM, SystemVerilog, SystemVerilog Assertions (SVA), JasperGold, VC Formal, Verilog-AMS, Real-number modeling (RNM), ATE
3mo
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HBM SIPI, Principal Engineer
Richardson or Folsom
$175k-$309k/yr OnsiteFull Time
7+ YOE7+ years SI/PI modeling and analysis experience, strong SI/PI fundamentals, experience with ANSYS/Synopsys/Cadence/Keysight, scripting with TCL/Python preferred, experience with 2.5D/3D packaging and high-bandwidth interfaces preferred.
ANSYS, Synopsys, Cadence, Keysight, TCL, Python
2mo
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Principal Analog Design Engineer — Mixed-Signal PHY (Clocking / High-Speed I/O)
Boise or Folsom or Richardson or San Jose
$159k-$347k/yr OnsiteFull Time
10+ YOE10+ years analog/mixed-signal IC design; PLL/DLL/clocking; transistor-level simulations; analog-digital interfaces; lab data correlation
HSpice
4d
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Developer
Sacramento County, California, United States
$9k-$12k/mo HybridFull Time
Technical expert for development, implementation, and support of enterprise IT systems; resolving complex system and interface issues and coordinating with stakeholders and vendors.
Angular JS, C#, Java, JavaScript, SQL, MySQL, Node JS, Visual Basic, Oracle PL/SQL, Oracle Database, CSS, HTML, COTS, Sass System, Ticketing System Tools, Code Management Tools, Agile, Waterfall
2mo
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SMTS Analog Design Engineer, Mixed-Signal PHY (Clocking & High-Speed I/O)
Boise or Folsom or Richardson or San Jose
$159k-$347k/yr OnsiteFull Time
10+ YOEBS/MS/PhD in EE; 10+ years analog/mixed-signal IC design with tape-out; deep clocking (PLL/DLL/CDR) expertise; transistor-level simulation with HSpice; strong jitter analysis and analog-digital interface experience.
HSpice, Verilog-AMS, Real-number modeling (RNM)
1mo
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Senior Technologist, Hardware Development Engineering -
Roseville, California, United States
$177k-$235k/yr OnsiteFull Time
Expert-level hardware engineer with hands-on board and ASIC integration experience, high-speed interface and SI/PI expertise, lab bring-up and root-cause debug, and cross-functional technical leadership.
Cadence, Altium, Mentor, IBIS, AMI, S-parameters, SPICE, Oscilloscope, BERT, Network Analyzer, Spectrum Analyzer, JTAG, PRBS, IBERT
3w
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Senior PACS Administrator & Imaging Informatics Lead (Hybrid, Greater LA and San Gabriel Valley)
United States or Sacramento or Los Angeles
$102k-$130k/yr RemoteFull Time
7+ YOECIIP required, 7+ years PACS administration in multi-site/enterprise environments, bachelor’s (or equivalent), experience with PACS/RIS, VNA, HL7/DICOM integrations, interface engines (Mirth Connect/Rhapsody/Cloverleaf), vendor dictation systems, SQL/server administration, and product ownership experience.
NovaRad, NovaRIS, Mirth Connect, MModal, Hyland (Acuo), IBM, Fujifilm, Sectra, Nuance PowerScribe, Dolbey, GE Centricity, Philips IntelliSpace, Intelerad, Fujifilm Synapse, Agfa, IBM Watson Health, Rhapsody, Cloverleaf, InterSystems HealthShare, DICOM, HL7, SQL
4d
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Student Assistant - Technician/Field Work - Audio Engineering Intern - Remote
Sacramento or Sonoma County
$17/hr RemoteMultiple Commitments Available
Current college enrollment in related major, proficiency with Mac hardware and DAWs (Logic Pro/Pro Tools/Adobe Audition), experience with microphones and audio interfaces, ability to travel to field sites, valid driver’s license, portfolio of podcast/audio work.
Mac OS, MacBook Pro, Logic Pro, Pro Tools, Adobe Audition, iZotope