2mo
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IP Design Engineer
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Strong RTL design skills, FPGA/ASIC knowledge, and collaboration across global teams. Proficiency in Verilog/SystemVerilog and scripting; excellent English communication.
Verilog, SystemVerilog, UVM, OVM, Python, Perl, Tcl, Shell, EDA Tools, Synopsys, Primetime, VCS, Cadence Virtuoso
1mo
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RTL / Circuit IP Design Engineer
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Design and implement RTL/IP features; strong RTL/Verilog/System Verilog, UVM, UPF, SAPR, and simulation/debugging skills; scripting (Python/Perl/Ruby/Makefile/shell); Bachelors or Masters in computer/electrical engineering required.
RTL, UVM, Linux, Windows, Verilog, System Verilog, Python, Perl, Ruby, Makefile, shell, HLS, SAPR, UPF
3w
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Infection Prevention Nurse IP
Capitola, California, United States
$90k-$120k/yr OnsiteFull Time
California RN or LVN in good standing; knowledge of infection control, regulations, and antibiotic stewardship; APIC infection control certification preferred; Microsoft Office/Excel and PCC skills; strong communication and decision-making.
Microsoft Office, Microsoft Excel, PCC
5d
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Infection Prevention Nurse IP
Campbell, California, United States
$95k/hr OnsiteFull Time
California RN or LVN in good standing; knowledge of infection control, ability to make independent decisions, strong communication and computer skills; APIC certification preferred.
Microsoft Office, Microsoft Excel, PCC
2mo
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DFx Methodology Architect
San Jose, California, United States
OnsiteFull Time
Bachelor or Master in computer engineering or Electrical Engineering; experience with RTL design, DFx, IP development, and scripting languages.
Perl, TCL, Python, Verilog
2mo
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Senior System RTL Designer/Architect
San Jose, California, United States
$203k-$348k/yr HybridFull Time
Senior-level system RTL design with IP architecture focus; strong communication and collaboration skills; experience balancing performance, power, and area.
1mo
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ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
Cupertino or Austin
$157k-$213k/yr OnsiteFull Time
Bachelor's in Electrical Engineering (required), experience debugging and verifying designs from IP to SoC, proficiency in SystemVerilog, strong analytical and problem-solving skills.
SystemVerilog, Python, Perl
2mo
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High Speed Mixed Signal Circuit Design Engineer
San Jose, California, United States
HybridFull Time
8+ YOEDesign and analyze high-speed analog/mixed-signal circuits; Cadence tool expertise; 8+ years in CMOS analog; MS in EE; production-ready IP development.
Cadence Virtuoso, Cadence Spectre, Cadence Incisive, Calibre, EMX, Totem EM/IR
2w
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Product Planning Engineer– DSP / RF
San Jose, California, United States
$160k-$240k/yr HybridFull Time
Experienced in DSP, RF, AI/ML and mixed-signal systems; translating system-level requirements into product and IP definitions; bachelor’s or master’s in engineering or related field preferred.
1w
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Sr. Formal Verification Engineer, Annapurna Labs
Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
7+ YOEBachelor's in CS/EE,7+ years formal verification experience as IP/block owner, expertise in abstraction and end-to-end checking, RTL and microarchitecture comprehension, and coding/scripting skills.
C, C++, C#, Node.JS, Java, Python, PHP, Ruby
3w
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
4d
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PLL Design/ Integration Staff Engineer - Adaptive Computing Group
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Strong IC design and manufacturing background with analog/digital IP integration (PLLs, LDOs), post-silicon validation experience, SystemVerilog modeling, Vivado or similar tool experience; MS preferred.
Vivado, SystemVerilog
1w
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System Development Engineer, AWS Manufacturing Infrastructure Services
Cupertino, California, United States
$149k-$201k/yr OnsiteFull Time
3+ YOEBachelor's in CS or equivalent,3+ years software and systems engineering,experience with networking (TCP/IP,DNS,DHCP),Linux,programming in C++,C#,Java,Python,Golang,automation and infrastructure design.
C++, C#, Java, Python, Golang, PowerShell, Ruby, Perl, PHP, Bash, Shell, TCP/IP, DNS, DHCP, VLANs, EC2, VPC, IAM, Outposts, CloudWatch, S3, Prometheus, Grafana, PXE, IPMI, BMC