1mo
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Staff Analog Layout Engineer
San Jose or Hsinchu
OnsiteFull Time
3+ YOESenior/Staff level IC layout engineer with 3-8+ years in deep-submicron analog/RF layouts; strong EDA/tool experience and EM/IR knowledge.
Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV
3w
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Principal Design Engineer
San Jose or Cary
$137k-$254k/yr OnsiteFull Time
1+ YOEBS/MS/PhD in Electrical Engineering with 7/5/1+ years respectively; experience with Cadence Innovus/Tempus/QRC/Voltus/Pegasus and Palladium/Protium; Linux and Shell/Perl/TCL scripting; RTL synthesis, floorplanning, timing closure, IR drop, and industry interfaces (PCIe, DDR, LPDDR, SRAM, UCIe).
Innovus, Tempus, QRC, Voltus, Pegasus, Palladium, Protium, Linux, Shell, Perl, TCL
4w
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Physical IC Design Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOE12+ years experience in full physical design cycle (RTL to tape-out). Bachelor’s in Electrical/Electronics Engineering, Tcl/Perl scripting, proficiency with EDA tools, timing closure, EM/IR analysis, and strong communication skills.
Tcl, Perl, EDA Tools
1w
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Senior Principal Hardware Engineer
San Jose or Raleigh
$137k-$254k/yr OnsiteFull Time
5+ YOEExperience driving physical design from synthesis to tape-out, expertise in floorplan/PNR/clocking/timing/IR-EM, familiarity with advanced nodes and scripting (PERL, Python, TCL, Shell).
PERL, Python, TCL, Shell
2mo
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Power Systems Design Engineer
San Jose, California, United States
OnsiteFull Time
8+ YOEBachelor’s in Electrical Engineering; 8+ years in power supply design for high-power processors; multi-phase power, 48V input conversion; PCB IR drop and power loss simulations; Cadence Voltus familiarity; willingness to apply even if not meeting every qualification.
Cadence Voltus IC Power Integrity Solution
2w
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Senior Software Engineer - Static Analysis
San Jose, California, United States
RemoteFull Time
7+ YOE7+ years software engineering (4+ in static/program analysis or compiler infrastructure); deep knowledge of control/data-flow, call graph construction, inter-procedural and taint/reachability analysis; strong Java/Go/C++ skills; IR/bytecode/AST experience; technical ownership.
Java, Go, C++, LLVM, MLIR, SSA, IR, bytecode, ASTs, CI/CD
1w
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Physical Design Engineer
San Jose, California, United States
$150k-$250k/yr OnsiteFull Time
7+ YOE7+ years physical design experience (synthesis, PnR, STA, timing convergence, physical verification); Bachelor's in EE/CE/CS or equivalent experience; proficiency with Innovus, Tempus, Quantus, TCL; experience with EM/IR, PDN, LEC and sub-7nm/SoC design.
Innovus, Tempus, Quantus, TCL, Cadence, Synopsys
1mo
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Power Integrity Engineer-Silicon
San Jose, California, United States
OnsiteFull Time
7+ YOE10+ years PI experience with bachelor’s (or 7+ with advanced degree); deep power integrity expertise for 2.5D/3D packaging, PDN design, transient/EM/IR analysis, simulation tool proficiency, and cross-functional leadership.
Ansys SIwave, HFSS, Cadence Sigrity, Apache RedHawk, Voltus, Keysight ADS
1mo
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Staff Compiler Engineer - PyTorch + Kernel DSLPLATE
San Jose, California, United States
$163k-$253k/yr OnsiteFull Time
10+ YOEBS with 10+ yrs, MS with 8+ yrs, or PhD with 5+ yrs; experience in Triton/Helion/MLIR/XLA/TVM/Inductor/IREE/CUTLASS; kernel DSL/IR design; MLIR; PyTorch backends; kernel autotuning; HPC/NUMA; open-source contributions.
Triton, Helion, MLIR, XLA, TVM, Inductor, IREE, CUTLASS, PyTorch, LLVM/MLIR
1mo
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Senior Power Integrity (PI) Analysis Engineer
San Jose or Austin
$152k-$255k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE, 5+ years PI experience on advanced nodes (sub-7nm), expertise in IR-drop analysis, hierarchical multi-voltage PI, CPF/UPF, and strong scripting skills.
Cadence Voltus, Synopsys RedHawk-SC, Tcl, Python, Perl
1w
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Software Engineer - AI Agent Memory Infrastructure
San Jose, California, United States
OnsiteFull Time
Bachelor's in CS or related, strong distributed systems and IR/AI infrastructure experience, proficient in Go/Python/C++, familiarity with embeddings/RAG and memory systems.
Go, Python, C++, mem0, memOS, memU
1w
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Senior Software Engineer - AI Agent Memory Infrastructure
San Jose, California, United States
OnsiteFull Time
Bachelor's in CS/AI/Data Science, strong experience in distributed systems/databases/IR or AI infrastructure, proficiency in Go/Python/C++, familiarity with LLM applications and memory systems.
Go, Python, C++, mem0, memOS, memU
1w
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AI software Engineer Project Intern (Transaction Platform) - 2026 Start (BS/MS)
San Jose, California, United States
OnsiteInternship
Currently pursuing BS/MS in Computer Science or related field; strong programming and software engineering fundamentals; hands-on experience with AI systems (IR, LLM apps, agents, RAG); familiarity with backend/frontend development; strong problem-solving and communication.
Java, React, GitLab, Meego, CI/CD
2w
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Performance Research Engineer (multiple levels)
San Jose or Pittsburgh
$180k-$250k/yr OnsiteFull Time
Hands-on software development with hardware, exposure to RISC/DSP/GPU platforms, CUDA/HIP, C/C++, familiarity with PTX/LLVM IR/MLIR, HW simulation experience, domain expertise in ML/signal/video/audio/robotics, and a minimum Master's in a technical field.
CUDA, HIP, PTX, LLVM IR, MLIR, C, C++
1w
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Edge ML Software Engineer (Compiler-PICO) - San Jose
San Jose, California, United States
OnsiteFull Time
3+ YOEMaster's in CS/EE/CE or equivalent,3+ years compiler/ML systems experience,strong C/C++ or Rust,knowledge of compiler IR, graph transforms, memory planning, and deep learning model structures.
torch.compile, MLIR, XLA, IREE, TVM, C, C++, Rust
3mo
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Failure Analysis Technician
San Jose, California, United States
$40-$55/hr OnsiteFull Time
High school diploma required; electronics/Materials science preferred; experience in failure analysis helpful; responsibilities include sample preparation, FA engineering support, documentation.
Optical inspection, X-ray, Decapsulation, Reballing, IR, UV inspections, SEM, FIB
3w
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Physical Design Technical Leader
San Jose, California, United States
$179k-$286k/yr OnsiteFull Time
10+ YOE10+ years physical design and flow development experience; advanced-node (4nm/3nm/2nm) and low-power design expertise; familiarity with DRC/LVS, timing closure, IR/EM, floorplanning; CoWoS/EMIB/3DIC experience a plus.
EDA, RTL, GDSII, CoWoS-S, CoWoS-L, EMIB, 3DIC
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