6 memory controller verification engineer jobs at 4 companies in United States
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Senior Memory Controller Verification Engineer
Santa Clara or Austin or Westford or Hillsboro or Seattle
$168k-$311k/yr HybridFull Time
6+ YOERequires BS/MS or equivalent experience, 6+ years of complex ASIC verification, SystemVerilog and UVM expertise, and experience with verification and debugging tools. C/C++, scripting, and memory controller experience preferred.
VCS, Debussy, GDB, SystemVerilog, UVM, C, C++, Python, Perl, shell, FPGA, RTL
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Senior Memory Controller Verification Engineer
Santa Clara or Austin or Westford or Hillsboro or Seattle
$168k-$311k/yr HybridFull Time
6+ YOE6+ years ASIC verification experience, SystemVerilog/UVM, simulation and debug tool experience (VCS, Debussy, GDB), strong C/C++ and scripting (Python/Perl/shell), BS/MS or equivalent.
VCS, Debussy, GDB, System Verilog, UVM, C, C++, Python, Perl, shell
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Senior Memory Controller Verification Engineer
Santa Clara or Westford or Austin or Hillsboro or Seattle
$168k-$311k/yr HybridFull Time
6+ YOE6+ years ASIC verification experience, BS/MS or equivalent, SystemVerilog/UVM experience, familiarity with VCS/Debussy/GDB, C/C++ and scripting (Python/Perl/shell), strong debugging and teamwork skills.
VCS, Debussy, GDB, System Verilog, UVM, C, C++, Python, Perl, Shell
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Staff Memory Controller Architecture and Design Engineer
San Diego, California, United States
$140k-$210k/yr OnsiteFull Time
4+ YOEBachelor's (or higher) in science/engineering with 4+ yrs ASIC design experience (or equivalent), experience with architecture/design tools, scripting/programming, design verification, and collaboration with senior leadership.
RTL to GDS Flow, Virtuoso
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Digital Verification
Austin, Texas, United States
$166k/yr OnsiteFull Time
5+ YOEBachelor's degree in engineering and 5 years of progressive experience. Requires SystemVerilog, C/C++, ARM and DSP architectures, memory controllers, SoC verification, Cadence, gate-level simulation, and IP-level verification.
SystemVerilog, C, C++, ARM, DSP, Cadence, UVM
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Sr. Principle Design Engineer
Austin, Texas, United States
OnsiteFull Time
10+ YOEBS/MS in Electrical or Computer Engineering,10-12 years experience in design verification, UVM environment development, DDR/LPDDR/AXI/CHI-E knowledge, memory controller verification experience.
UVM