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Multimedia Designer
Modesto, California, United States
$33-$42/hr OnsiteFull Time
2+ YOE2+ years graphic design experience preferred; video and podcast production desirable; associate degree in design/communications preferred; valid California driver's license; ability to produce ADA-compliant multimedia content.
Windows, Word
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Data Scientist - Multimedia
San Jose, California, United States
$95k-$240k/yr OnsiteFull Time
Experience in data science focused on mobile app performance and creation-oriented user behavior; proficient in SQL and Python; experience with Hive or Spark; strong A/B testing, metric design, and causal inference skills.
SQL, Python, Hive, Spark
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SoC Digital Design Engineer, Multimedia Lab
San Jose, California, United States
$156k-$317k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CS or related, 1+ years front-end digital design, mastery of Verilog/SystemVerilog, experience with front-end EDA tools, scripting (Python/Perl/Tcl/Makefile).
Verilog, SystemVerilog, Spyglass, Design Compiler, PrimeTime, Python, Perl, Tcl, Makefile, UPF, SDC, STA, FPGA, ASIC
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Senior SoC Digital Design Engineer, Multimedia Lab
San Jose, California, United States
$213k-$450k/yr OnsiteFull Time
3+ YOEBachelor's in EE/CS or related, 3+ years front-end digital/SoC design, mastery of Verilog/SystemVerilog, experience with front-end EDA tools, scripting (Python/Perl/Tcl/Makefile), and low-power design techniques.
Verilog, SystemVerilog, Spyglass, Design Compiler, PrimeTime, Python, Perl, Tcl, Makefile, UPF, SDC, STA
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ASIC Design Engineer (Video Silicon IP) - Multimedia Lab
San Jose, California, United States
OnsiteFull Time
2+ YOEM.S./Ph.D. in EE/CE, 2+ years ASIC front-end RTL ownership, proficiency in SystemVerilog/Verilog or HLS, familiarity with UVM/DPI/C++, Python scripting, and VLSI design concepts.
SystemVerilog, Verilog, High level Synthesis (HLS), UVM, DPI, C++, Python, AXI, APB, EDA, GitHub Copilot, Claude, ChatGPT, FPGA
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Sr. ASIC Design Engineer (Video Silicon IP) - Multimedia Lab
San Jose, California, United States
OnsiteFull Time
5+ YOEM.S. or Ph.D. in EE/CE, 5+ years ASIC front-end RTL ownership, SystemVerilog/HLS proficiency, UVM/DPI/C++ familiarity, and Python scripting for EDA flows.
FPGA, ASIC, SystemVerilog, Verilog, High Level Synthesis (HLS), UVM, DPI, C++, Python, GitHub Copilot, Claude, ChatGPT