2mo
Save
Mark Applied
Hide
NOC Engineer - Dedicated (Austin, TX)
Austin or Exeter
HybridFull Time
1+ YOE1+ years technical experience in network/telecommunications operations; high school diploma required; associate's degree preferred; familiarity with Cisco platforms and monitoring tools; strong documentation and communication skills.
Cisco, Splunk, SolarWinds, ITSM
2d
Save
Mark Applied
Hide
Lead AI NOC Engineer
Somerville or Fort Mill or Austin or Boston or New York or Tempe or San Diego
$94k-$171k/yr HybridFull Time
8+ YOE5+ Mgmt8+ years in IT operations/SRE, 5+ years leading incident management; bachelor\u0002s or equivalent; hands-on Dynatrace and ServiceNow experience; cloud (AWS/Azure/GCP) expertise; ITIL/SRE/AIOps experience.
Dynatrace, ServiceNow, AWS, Azure, GCP
2w
Save
Mark Applied
Hide
NOC Engineer III, Incident Management Team
Austin, Texas, United States
$134k-$152k/yr OnsiteFull Time
GFiber: An internet service provider building and operating fiber networks and related network services.
3+ YOEBachelor's degree or equivalent experience, 3+ years routing protocol and network troubleshooting experience, familiarity with BGP/OSPF/TCP-IP, incident management, ability to work non-standard hours.
TCP/IP, BGP, OSPF, CWDM, DWDM, Ciena Waveserver, Juniper MX, Juniper QFX, Juniper PTX, Nokia 7x50, Adtran PON, Nokia PON, OLT, ONT, OSS Functionality
1mo
Save
Mark Applied
Hide
Engineer NOC I (Austin, TX, US, 78727)
Austin, Texas, United States
$52k-$97k/yr OnsiteFull Time
3+ YOEAssociate degree or 3+ years related experience; experience with network automation, NMS administration, monitoring, SLA adherence, and customer-focused service delivery.
NMS, ISO 9001, ISO 20000, IGT 27001
2mo
Save
Mark Applied
Hide
Lead RTL Design Engineer
Austin or Pittsburgh or San Jose
$160k-$250k/yr OnsiteFull Time
8+ YOE8+ years RTL design with tape-out ownership; SystemVerilog; on-chip networks, memory subsystems, NoC; low-power design; DV collaboration; silicon bring-up.
SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC, STA, ATPG, DFT, memory compiler
2w
Save
Mark Applied
Hide
Interconnect Micro-architect/RTL Design Engineer
Austin, Texas, United States
HybridFull Time
Experienced RTL engineer with Verilog/SystemVerilog expertise, microarchitecture design for interconnect/NoC, debugging skills, and familiarity with Python,C/C++; BS/MS/PhD in electrical or computer engineering preferred.
Verilog, SystemVerilog, Python, C, C++
4w
Save
Mark Applied
Hide
Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
OnsiteFull Time
Staff-level hardware engineer with experience designing interconnects, cache/coherency, RTL generators using Chisel/Scala; proficiency in Verilog/System Verilog/VHDL and hardware-software engineering practices; BS/MS in EE/CE/CS or equivalent.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, NoC, AXI, AHB, APB, CHI, Bluespec, Git, GitHub, Jira, Confluence
3w
Save
Mark Applied
Hide
Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$179k-$219k/yr OnsiteFull Time
Design and implement TileLink interconnect, cache controllers and RTL generators; knowledge of cache coherency, NoC/interconnects, bus protocols (AXI/AHB/APB/CHI), RTL (Verilog/SystemVerilog/VHDL), and strong software engineering skills (Scala/Chisel preferred).
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, AXI, AHB, APB, CHI, Git, GitHub, Jira, Confluence
2w
Save
Mark Applied
Hide
Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
6+ YOE6+ years ASIC verification experience with fabric/interconnect/NoC, strong SystemVerilog and UVM skills, knowledge of interconnect protocols (AMBA AXI, CHI), scripting (Python, Perl, TCL), and degree in computer/electrical engineering or equivalent experience.
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SVA
3w
Save
Mark Applied
Hide
VLSI RTL design engineer
Fort Collins or Austin
$106k-$183k/yr HybridFull Time
3+ YOEBS/MS in EE/CS/CSE with 3+ years hardware design experience; experience in Digital RTL design, Verilog HDL, SRAM/Coherent Cache/NOC, scripting; strong communication and problem-solving skills.
Verilog HDL
3w
Save
Mark Applied
Hide
Principal Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$231k-$283k/yr OnsiteFull Time
Expertise in interconnects, cache/coherency, NoC and bus protocols (AXI, AHB, APB, CHI, CXL, UCIe); RTL design in Verilog/SystemVerilog/VHDL; experience with Chisel/FIRRTL/Scala preferred; BS/MS in EE/CE/CS or equivalent.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, Git, GitHub, Jira, Confluence
3d
Save
Mark Applied
Hide
SoC Logic Design Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
3+ YOEExperience in RTL/Verilog logic design, SoC integration, low-power and timing optimization, Clock Domain Crossing and NoC architectures, AMBA protocols; bachelor's or master's in EE/CE with relevant years of experience.
RTL, Verilog, AMBA, CHI, AXI, AHB, APB, Network-on-Chip (NoC), Clock Domain Crossing
4w
Save
Mark Applied
Hide
Network Operations Center Engineer
Austin, Texas, United States
$100k-$140k/yr OnsiteFull Time
2+ YOE2+ years NOC/SOC/telecom or mission-critical operations experience; networking fundamentals, shift-based operations, ticketing and monitoring proficiency, strong troubleshooting and communication; industry certs preferred.
Cisco, Palo Alto, BMS, EPMS, SCADA, DCIM
2w
Save
Mark Applied
Hide
Manager of Field Applications Engineering, USA
Santa Clara or Austin
OnsiteFull Time
10+ YOE5+ MgmtBachelor's in EE/CE/STEM required; 10+ years in semiconductor/silicon IP/networking and 5+ years managing customer-facing engineering teams; deep NoC/AMBA/PCIe/CXL knowledge and EDA tool familiarity.
Synopsys, Cadence, Siemens