1mo
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NOC Engineer - Dedicated (Austin, TX)
Austin or Exeter
HybridFull Time
1+ YOE1+ years technical experience in network/telecommunications operations; high school diploma required; associate's degree preferred; familiarity with Cisco platforms and monitoring tools; strong documentation and communication skills.
Cisco, Splunk, SolarWinds, ITSM
1w
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NOC Engineer III, Incident Management Team
Austin, Texas, United States
$134k-$152k/yr OnsiteFull Time
GFiber: An internet service provider building and operating fiber networks and related network services.
3+ YOEBachelor's degree or equivalent experience, 3+ years routing protocol and network troubleshooting experience, familiarity with BGP/OSPF/TCP-IP, incident management, ability to work non-standard hours.
TCP/IP, BGP, OSPF, CWDM, DWDM, Ciena Waveserver, Juniper MX, Juniper QFX, Juniper PTX, Nokia 7x50, Adtran PON, Nokia PON, OLT, ONT, OSS Functionality
1mo
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Engineer NOC I (Austin, TX, US, 78727)
Austin, Texas, United States
$52k-$97k/yr OnsiteFull Time
3+ YOEAssociate degree or 3+ years related experience; experience with network automation, NMS administration, monitoring, SLA adherence, and customer-focused service delivery.
NMS, ISO 9001, ISO 20000, IGT 27001
2mo
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Lead RTL Design Engineer
Austin or Pittsburgh or San Jose
$160k-$250k/yr OnsiteFull Time
8+ YOE8+ years RTL design with tape-out ownership; SystemVerilog; on-chip networks, memory subsystems, NoC; low-power design; DV collaboration; silicon bring-up.
SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC, STA, ATPG, DFT, memory compiler
1w
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Interconnect Micro-architect/RTL Design Engineer
Austin, Texas, United States
HybridFull Time
Experienced RTL engineer with Verilog/SystemVerilog expertise, microarchitecture design for interconnect/NoC, debugging skills, and familiarity with Python,C/C++; BS/MS/PhD in electrical or computer engineering preferred.
Verilog, SystemVerilog, Python, C, C++
3w
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
OnsiteFull Time
Staff-level hardware engineer with experience designing interconnects, cache/coherency, RTL generators using Chisel/Scala; proficiency in Verilog/System Verilog/VHDL and hardware-software engineering practices; BS/MS in EE/CE/CS or equivalent.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, NoC, AXI, AHB, APB, CHI, Bluespec, Git, GitHub, Jira, Confluence
2w
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$179k-$219k/yr OnsiteFull Time
Design and implement TileLink interconnect, cache controllers and RTL generators; knowledge of cache coherency, NoC/interconnects, bus protocols (AXI/AHB/APB/CHI), RTL (Verilog/SystemVerilog/VHDL), and strong software engineering skills (Scala/Chisel preferred).
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, AXI, AHB, APB, CHI, Git, GitHub, Jira, Confluence
1w
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Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
6+ YOE6+ years ASIC verification experience with fabric/interconnect/NoC, strong SystemVerilog and UVM skills, knowledge of interconnect protocols (AMBA AXI, CHI), scripting (Python, Perl, TCL), and degree in computer/electrical engineering or equivalent experience.
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SVA
3w
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VLSI RTL design engineer
Fort Collins or Austin
$106k-$183k/yr HybridFull Time
3+ YOEBS/MS in EE/CS/CSE with 3+ years hardware design experience; experience in Digital RTL design, Verilog HDL, SRAM/Coherent Cache/NOC, scripting; strong communication and problem-solving skills.
Verilog HDL
2w
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Principal Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$231k-$283k/yr OnsiteFull Time
Expertise in interconnects, cache/coherency, NoC and bus protocols (AXI, AHB, APB, CHI, CXL, UCIe); RTL design in Verilog/SystemVerilog/VHDL; experience with Chisel/FIRRTL/Scala preferred; BS/MS in EE/CE/CS or equivalent.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, Git, GitHub, Jira, Confluence
1w
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Manager of Field Applications Engineering, USA
Santa Clara or Austin
OnsiteFull Time
10+ YOE5+ MgmtBachelor's in EE/CE/STEM required; 10+ years in semiconductor/silicon IP/networking and 5+ years managing customer-facing engineering teams; deep NoC/AMBA/PCIe/CXL knowledge and EDA tool familiarity.
Synopsys, Cadence, Siemens