8 packaging design jobs at 6 companies in Eloy, AZ
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Advanced Packaging Design Engineer
Santa Clara or Chandler
$192k-$287k/yr OnsiteFull Time
5+ YOEBS/MS/PhD in engineering,5-10 years advanced packaging design experience, expertise with Cadence APD, high-speed interfaces, substrate and assembly processes, and cross-functional collaboration.
Cadence APD, AutoCAD
2w
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Silicon Packaging Design Engineer
Phoenix or Hillsboro or Chandler
$164k-$232k/yr OnsiteFull Time
10+ YOEMaster's in EE/ME, 10+ years PCB layout with Cadence Allegro and Cadence Constraint Manager, 5+ years hardware development (schematic, SI, power delivery), PCB manufacturability and DRC expertise, strong analytical and collaboration skills.
Cadence Allegro, Cadence Constraint Manager, Siemens Xpedition, Product Lifecycle Management (PLM)
2mo
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Senior Design Lead (122083)
Chandler or Hillsboro
OnsiteContract
10+ YOEBachelor's or Master's in Electrical/Electronics Engineering; ~10+ years IC packaging/package design for senior level (4–6+ years mid); hands-on experience with Siemens (Mentor) Xpedition or Cadence Allegro/APD, physical/substrate design, SI/PI-aware design, DFM and design rule compliance.
Siemens (Mentor) Xpedition (XPD), Cadence Allegro, Advanced Package Designer (APD / SiP)
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Mechanical Design Engineer - Semiconductor Packaging
Phoenix or Chandler
$106k-$149k/yr OnsiteFull Time
1+ YOEBachelor's in mechanical engineering or STEM,1+ year CAD and mechanical design experience,ability to interpret technical drawings and specifications.
SolidWorks, Siemens NX, AutoCAD
5d
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SOC Design Engineer
Chandler or Cambridge
$198k-$268k/yr HybridFull Time
Experienced electronics engineer with PCB and silicon package co-design expertise, high-speed design, SI/PI analysis, PCB fabrication, EDA tools, and embedded compute systems knowledge.
PCIe, LPDDR, PTH, HDI, VIA, Cadence OrCAD, Cadence Allegro, ANSYS, Siemens EDA
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Principal PCB - Package co-design Architect
Chandler, Arizona, United States
$250k-$338k/yr HybridFull Time
Deep SoC and embedded compute expertise; high-speed I/O, PCB and package co-design, SI/PI, EDA tools, fabrication, routing, manufacturability, and cross-functional architecture experience required.
PCIe, LPDDR5, LPDDR6, CSI, DSI, FPGA, PMIC, Cadence OrCAD, Cadence Allegro, ANSYS, Siemens EDA
2w
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Designer I/II
Casa Grande, Arizona, United States
OnsiteFull Time
2+ YOEPrepare and modify plant design change packages, gather and develop engineering data, support design documents and walk‑downs; requires CADD coursework and design experience.
CADD, Windows
3w
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Chief Technology Officer (CTO) – AIS
Chandler, Arizona, United States
$165k-$255k/yr OnsiteFull Time
15+ YOE15+ years leadership in semiconductor/interconnect/advanced packaging; deep SI/PI and socket/interconnect design expertise; proven R&D-to-HVM scaling; executive global engineering leadership; DFA and factory automation experience.