Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
40 packaging design engineer jobs at 17 companies in Pacific Grove, CA
3w
Save
Mark Applied
Hide
Packaging Design Engineer
San Jose or San Diego
HybridFull Time
Experienced package engineer with CAD/simulation tool proficiency, package/PCB layout and power integrity expertise, scripting ability, and engineering degree.
Cadence, SKILL, Ansys, AutoCAD
3mo
Save
Mark Applied
Hide
Packaging Design Engineer I
San Jose or Hayward or Texas
OnsiteFull Time
TransPak: Packaging solutions provider
2+ YOEBachelor’s in mechanical/manufacturing/industrial/packaging engineering; 2-3 years mechanical/structural design experience; CAD (SolidWorks/AutoCAD); GD&T knowledge; packaging design and testing experience; strong communication.
SolidWorks, AutoCAD, NX, BOM, 3D modeling, 2D drawings, GD&T
2mo
Save
Mark Applied
Hide
Manufacturing Design Engineer (MDE) - Packaging
Cupertino, California, United States
OnsiteFull Time
Managing R&D, selection, and implementation of manufacturing processes for consumer packaging parts and assemblies; strong product and process engineering skills.
1w
Save
Mark Applied
Hide
Packaging Tech Lead Design Engineer
San Jose, California, United States
$185k-$240k/yr OnsiteFull Time
5+ YOEBachelor's degree in electrical or computer engineering and 5+ years of digital design experience, including a full chip from specification to tapeout. Requires Verilog/SystemVerilog, RTL, synthesis, timing closure, CDC, lint, and low-power expertise.
Verilog, SystemVerilog, RTL, CDC, DFT, BIST, PCIe, CXL, Ethernet, NVLink, UALink, UCIe, COSMOS, SoC
2mo
Save
Mark Applied
Hide
Staff Semi Packaging Engineer
San Jose, California, United States
$130k-$188k/yr OnsiteFull Time
3+ YOEMaster's in a relevant engineering field + ≥3 years industrial IC/package experience; expertise in analog IC package/module design, reliability and BOM selection, CAD modeling, and process development (FMEA, SPC, DOE); OSAT collaboration experience.
CAD
2w
Save
Mark Applied
Hide
Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$136k-$213k/yr OnsiteFull Time
5+ YOEBachelor's degree in electrical engineering or related field and 5+ years of IC package layout and physical design experience. Requires package layout tools, advanced packaging, DFM, and physical verification expertise.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, Perl, ARM, TCL, Skill, Ravel, DRC
4w
Save
Mark Applied
Hide
Package Design Engineer
San Jose or Austin or Fort Collins
$122k-$195k/yr OnsiteFull Time
6+ YOEBSEE with 8+ years or MSEE with 6+ years in flip-chip BGA package design; knowledge of package signal and power integrity; Cadence APD and Cadence SKILL experience preferred; project management and collaboration skills.
Cadence APD, Cadence SKILL
1mo
Save
Mark Applied
Hide
IC Package Design Engineer
San Jose, California, United States
$153k-$219k/yr HybridFull Time
3+ YOEBachelor's (5+ years) or Master’s (3+ years) in Electrical Engineering or related field; experience in package/PCB/high-speed design, power delivery, and EDA tools; scripting (Python, Perl, TCL, shell) and strong collaboration skills.
EDA, Python, Perl, TCL, Shell
3mo
Save
Mark Applied
Hide
Advanced Packaging SI/PI Engineer
San Jose, California, United States
$150k-$275k/yr OnsiteFull Time
8+ YOEBachelor's or Master's in Electrical/Computer Engineering; 8+ years SI/PI experience on high-performance ASIC/accelerator platforms; PDN design, high-speed interfaces; proficiency with SI/PI tools; packaging/OSAT/ODM collaboration.
ANSYS HFSS, SIwave, Cadence Sigrity, Keysight ADS
1mo
Save
Mark Applied
Hide
Principal Package Design Engineer
San Jose, California, United States
$195k-$240k/yr HybridFull Time
5+ YOEMSc/PhD in engineering, 5+ years semiconductor packaging experience, expertise in advanced packaging architectures, reliability testing, thermal/mechanical/electrical analysis, OSAT collaboration, and project leadership.
Cadence Allegro Package Designer, Solid works, ANSYS, COMSOL, JMP, Minitab
2mo
Save
Mark Applied
Hide
Mechanical Design Engineer
Morgan Hill or Melbourne or Lowell or North America or Europe or Asia
$82k-$131k/yr OnsiteFull Time
5+ YOEMechanical engineering degree with 5+ years in electronics packaging/assembly, proficiency in SolidWorks/AutoCAD and thermal analysis (Icepak preferred), GD&T, machining, tolerance/material selection, vendor coordination, BOM and DFM experience.
SolidWorks, Icepak, AutoCAD, PCB layout viewers, GD&T
3w
Save
Mark Applied
Hide
Physical Design - SOC Top Lead
San Jose or Pittsburgh or Austin
$200k-$250k/yr OnsiteFull Time
8+ YOEEnd-to-end SOC top ownership including full-chip integration, timing closure, power/PDN analysis, physical verification, SI, clock/reset, DFT, package co-design, and tapeout readiness; advanced degree in EE and extensive PD experience.
Innovus, ICC2, Tempus, PrimeTime, RedHawk, Calibre, Voltus, TCL, shell, python
3mo
Save
Mark Applied
Hide
Software Engineer 6 - Ads Pricing & Packaging
Los Gatos or New York
$499k-$900k/yr OnsiteFull Time
10+ YOE10+ years software development experience (5+ years on inventory management); expertise in yield optimization, dynamic pricing, auction mechanics, rate card and packaging systems; API and data model design; technical leadership and strong communication.
VAST, OpenRTB
3mo
Save
Mark Applied
Hide
SPE Signal Integrity Engineer
Johns Creek or San Jose or Bangalore or Seoul
$134k-$249k/yr OnsiteFull Time
10+ YOESenior-level SI/PI engineer with 10+ years in DDR4/5, EM theory, and package design.
ADS, HFSS, Q3D/PowerSI, Spice
2mo
Save
Mark Applied
Hide
Staff Software Engineer, Pricing and Packaging Engineering
San Francisco or Denver or New York City or San Jose
$197k-$247k/yr HybridFull Time
8+ YOE8+ years building large-scale backend platform systems (commerce/billing/subscriptions preferred); strong distributed systems, API design, SLO, and mentorship experience; proven delivery of multi-quarter projects.
1mo
Save
Mark Applied
Hide
Signal and Power Integrity Senior Application Engineer
San Jose, California, United States
$84k-$156k/yr OnsiteFull Time
1+ YOEBachelor's or Master's in Electrical/Electronics Engineering, 1+ years related experience, strong background in signal, power, and electromagnetics for package and PCB design, excellent communication and presentation skills.
Sigrity, Clarity, PCB Editor, ICP, Cadence Allegro
3mo
Save
Mark Applied
Hide
Signal Integrity & Power Integrity Principal Engineer
San Jose, California, United States
$187k-$270k/yr OnsiteFull Time
15+ YOE15+ years SI/PI experience; Bachelor's in Electrical/Computer Engineering; expertise in SI/PI for silicon/package/board; strong with HFSS/HSPICE/Sigrity/ADS; scripting in Python/MATLAB; design tool experience
ANSYS HFSS, Synopsys HSPICE, Cadence Sigrity, Keysight ADS, Mentor Graphics, Cadence Allegro, Python, MATLAB
2mo
Save
Mark Applied
Hide
Power Integrity Engineer-Silicon
San Jose, California, United States
OnsiteFull Time
7+ YOE10+ years PI experience with bachelor’s (or 7+ with advanced degree); deep power integrity expertise for 2.5D/3D packaging, PDN design, transient/EM/IR analysis, simulation tool proficiency, and cross-functional leadership.
Ansys SIwave, HFSS, Cadence Sigrity, Apache RedHawk, Voltus, Keysight ADS