11 packaging design engineer jobs at 4 companies in Seaside, CA
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Packaging Design Engineer
San Jose or San Diego
HybridFull Time
Experienced package engineer with CAD/simulation tool proficiency, package/PCB layout and power integrity expertise, scripting ability, and engineering degree.
Cadence, SKILL, Ansys, AutoCAD
2w
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Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$136k-$213k/yr OnsiteFull Time
5+ YOEBachelor's degree in electrical engineering or related field and 5+ years of IC package layout and physical design experience. Requires package layout tools, advanced packaging, DFM, and physical verification expertise.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, Perl, ARM, TCL, Skill, Ravel, DRC
2mo
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Mechanical Design Engineer
Morgan Hill or Melbourne or Lowell or North America or Europe or Asia
$82k-$131k/yr OnsiteFull Time
5+ YOEMechanical engineering degree with 5+ years in electronics packaging/assembly, proficiency in SolidWorks/AutoCAD and thermal analysis (Icepak preferred), GD&T, machining, tolerance/material selection, vendor coordination, BOM and DFM experience.
SolidWorks, Icepak, AutoCAD, PCB layout viewers, GD&T
1mo
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Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
10+ YOEBachelor's in EE or related, 10+ years IC package layout and physical design experience, expertise with advanced packaging (2.5D/3D, WLP, RDL, TSV), package DRC/DFM, and collaboration with SI/PI and manufacturing teams.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, TCL, Skill, Ravel
2w
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Sr. Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging
Cupertino or Austin or Los Angeles County
$183k-$248k/yr OnsiteFull Time
10+ YOEBachelor's degree in electrical engineering or related field, 10+ years of signal integrity, power integrity, and package design experience, advanced packaging expertise, and hands-on SI/PI and EM simulation tools experience.
Ansys RedHawk-SC 3DIC, Cadence Voltus, HFSS, Cadence Sigrity, PowerSI, PowerDC, Clarity, ADS, TDR, VNA, oscilloscope, PCIe, UCIe, SerDes, EMIB, CoWoS
3mo
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Software Engineer 6 - Ads Pricing & Packaging
Los Gatos or New York
$499k-$900k/yr OnsiteFull Time
10+ YOE10+ years software development experience (5+ years on inventory management); expertise in yield optimization, dynamic pricing, auction mechanics, rate card and packaging systems; API and data model design; technical leadership and strong communication.
VAST, OpenRTB
3w
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Sr. Mechanical Engineer, Annapurna Labs, Artificial Intelligence Hardware
Austin or Seattle or Cupertino
$159k-$248k/yr OnsiteFull Time
7+ YOEBS in mechanical engineering,7+ years mechanical and thermal design experience for electronics packaging/SoC,SoC thermal modeling, CFD/FEA, production fleet support, and cross-functional leadership.
Ansys Icepak, FloTherm, Cadence Celsius, PTC Creo, Solidworks, Bash, Shell, Linux, Python, Lua
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Principal Mechanical Engineer
San Jose, California, United States
$203k-$348k/yr OnsiteFull Time
Technical leadership in advanced semiconductor packaging including mechanical design, FEA/stress/warpage simulation, qualification and manufacturing ramp; MS/PhD preferred; hands-on with ANSYS Mechanical, Creo, SolidWorks.
ANSYS Mechanical, Creo, SolidWorks, FEA
2mo
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EMIR Engineer, Annapurna Labs - Cloud Scale Machine Learning
Austin or Cupertino
$136k-$213k/yr OnsiteFull Time
Experienced EM/IR engineer for SoC EMIR sign-off, power-grid design and analysis, EMIR flow setup, cross-domain IR analysis (die/package/board), EDA tool collaboration, and post-silicon correlation.
SystemVerilog, Make, FusionCompiler, Innovus, PrimePower, PrimeTime, ARM
3d
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2027 Undergrad ASIC Package Engineering Co-op/Intern
San Jose or Santa Clara
$64k-$96k/yr HybridInternship, Temporary
Current U.S. university bachelor's student in engineering or a related field; knowledge of circuits, package/PCB design, Perl, Python, SQL, semiconductor packaging, or Power BI encouraged.
Perl, Python, SQL, Power BI
3d
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2027 Masters ASIC Package Engineering Co-op/Intern
Santa Clara or San Jose
$83k-$125k/yr HybridInternship, Temporary
Current master's student in electrical, computer, mechanical, materials science, engineering science, or related field at a US university; knowledge of circuits, packaging, design software, scripting, or data tools preferred.
Perl, Python, SQL, Power BI