10 packaging design engineer jobs at 6 companies in Vancouver, WA
4w
Save
Mark Applied
Hide
Silicon Packaging Design Engineer
Phoenix or Hillsboro or Chandler
$164k-$232k/yr OnsiteFull Time
10+ YOEMaster's in EE/ME, 10+ years PCB layout with Cadence Allegro and Cadence Constraint Manager, 5+ years hardware development (schematic, SI, power delivery), PCB manufacturability and DRC expertise, strong analytical and collaboration skills.
Cadence Allegro, Cadence Constraint Manager, Siemens Xpedition, Product Lifecycle Management (PLM)
3mo
Save
Mark Applied
Hide
Silicon Packaging Design Engineer
Phoenix or Hillsboro
$106k-$200k/yr OnsiteFull Time
3+ YOEBachelor's degree with 3+ years or Master's with 2+ years in Electrical/Computer Engineering or STEM; experience with custom layout/EDA tools; silicon physical layout and interconnects; strong collaboration.
Virtuoso, Innovus, FusionCompiler, ICvalidator, Calibre
1d
Save
Mark Applied
Hide
Mechanical Product Design Engineer II
Portland, Oregon, United States
HybridFull Time
2+ YOEBachelor's degree in engineering and 2–4 years of related experience required. Requires CAD, engineering documentation, chassis packaging, communication, and general office application proficiency.
Microsoft Word, Microsoft Excel, Microsoft PowerPoint, CAD, NX, Imacs, Smaragd, ERS, Power BI, VBA
3d
Save
Mark Applied
Hide
Mechanical Product Design Engineer II
Portland, Oregon, United States
$86k-$110k/yr HybridFull Time
2+ YOEBachelor's degree in mechanical engineering or related discipline and 2–4 years of related experience. Requires CAD and engineering documentation proficiency; NX, vehicle packaging, and product development experience preferred.
Microsoft Word, Microsoft Excel, Microsoft PowerPoint, CAD, NX, IMACS, IMACS+, PLATON, ERS, Shainin RedX, Six Sigma, 8D, ZEUS, FRACAS
6d
Save
Mark Applied
Hide
Director of Package Design
Mountain View or Redmond or Hillsboro or Austin or Raleigh
$143k-$275k/yr HybridFull Time
3+ YOERequired: doctorate plus 3+ years, master's plus 6+ years, bachelor's plus 8+ years, or equivalent. Preferred: 15+ years semiconductor package experience and advanced packaging, CAD, simulation, supplier, and manufacturing expertise.
Cadence Allegro, EDA, BGA
1w
Save
Mark Applied
Hide
Signal and Power Integrity Engineer
Raleigh or Redmond or Austin or Hillsboro or Mountain View
$102k-$202k/yr HybridFull Time
1+ YOEMaster’s degree plus 1+ year or bachelor’s degree plus 2+ years in technical engineering; 5+ years of signal and power integrity, system design, electrical modeling, or silicon packaging experience preferred.
6d
Save
Mark Applied
Hide
Structural Designer
Hillsboro, Oregon, United States
$50k-$70k/yr HybridFull Time
1+ YOEHigh school or associate degree in architectural design, engineering design, or drafting; 1–2+ years using AutoCAD or Revit for engineering or architectural design packages; industrial design experience preferred.
AutoCAD, Revit, BIM, AI Large Language Models
3w
Save
Mark Applied
Hide
3D-IC Application Engineer
Austin or Boulder or Fremont or San Diego or Santa Clara or Wilsonville
$125k-$251k/yr HybridFull Time
4+ YOEMSEE/BSEE and 4+ years of design experience with advanced IC package or interposer layout. Requires package design tools, scripting, Windows/Linux, and strong presentation and customer skills.
Innovator 3D IC Layout, Innovator3D IC Integrator, Xpedition, Calibre, HyperLynx, Cadence APD/SiP, Siemens XSI/i3DI, Cadence OrbitIO/ISP, Synopsys 3DIC Compiler, Microsoft Excel, TSMC InFO, CoWoS, Intel EMIB, Foveros, ASE FoCUS, Amkor SWIFT, Samsung I/H/X-Cube, Verilog, LEF/DEF, GDS, OASIS, Sigrity, SIWave, ADS, Microsoft Word, Microsoft PowerPoint, VBS, Python, Tcl, Perl, Windows, Linux
1w
Save
Mark Applied
Hide
Principal CPU Architect - High-Performance and Physical Design
Santa Clara or Austin or Hillsboro
$272k-$431k/yr OnsiteFull Time
15+ YOERequires a BS/MS in engineering or computer science, 15+ years of relevant experience, extensive CPU architecture and high-frequency server CPU design expertise, and knowledge of power, process, circuit, and packaging technologies.
RTL, VLSI, SW, GPU, SoC
3w
Save
Mark Applied
Hide
Senior System and Manufacturing CoDesign Architect - Power, Thermal and Packaging
Santa Clara or Hillsboro
$196k-$368k/yr HybridFull Time
12+ YOEBS, MS, or PhD in electrical engineering, physics, or computer engineering; 12+ years of relevant experience; expertise in power delivery, thermal dissipation, current density, and cross-functional system-manufacturing design.
AI