26 packaging designer jobs at 15 companies in Gustine, CA

2mo
Save
Mark Applied
Hide
Packaging Design Engineer I
San Jose or Hayward or Texas
OnsiteFull Time
TransPak: Packaging solutions provider
2+ YOEBachelor’s in mechanical/manufacturing/industrial/packaging engineering; 2-3 years mechanical/structural design experience; CAD (SolidWorks/AutoCAD); GD&T knowledge; packaging design and testing experience; strong communication.
SolidWorks, AutoCAD, NX, BOM, 3D modeling, 2D drawings, GD&T
4w
Save
Mark Applied
Hide
Staff Semi Packaging Engineer
San Jose, California, United States
$130k-$188k/yr OnsiteFull Time
Analog Devices
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
3+ YOEMaster's in a relevant engineering field + ≥3 years industrial IC/package experience; expertise in analog IC package/module design, reliability and BOM selection, CAD modeling, and process development (FMEA, SPC, DOE); OSAT collaboration experience.
CAD
2mo
Save
Mark Applied
Hide
Photonic Packaging Engineer, Principal
San Jose, California, United States
OnsiteFull Time
Astera Labs
Astera LabsNASDAQ: ALAB: Designs connectivity solutions for cloud and AI infrastructure.
10+ YOEPh.D. or M.S. in EE, Physics, Materials Science, Mechanical Engineering, or related field; 10+ years in photonic packaging or related areas; strong expertise in high-speed packaging, thermal management, and optomechanical design.
3mo
Save
Mark Applied
Hide
Advanced Optical Packaging Design Tech Lead
San Jose, California, United States
$211k-$356k/yr OnsiteFull Time
MediaTek
MediaTekTaiwan Stock Exchange: 2454: Designs and develops system-on-chip solutions for electronic devices.
7+ YOEMaster's/PhD in engineering or related field with 7+ years in semiconductor/optoelectronic packaging, expertise in substrate design, hybrid bonding, warpage analysis, signal integrity, and cross-functional production enablement.
Cadence APD/Allegro, ANSYS, HFSS, CST, KLayout, COMSOL
3mo
Save
Mark Applied
Hide
Package Architect – Advanced Packaging & System Exploration
Boise or San Jose
$177k-$387k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
10+ YOEBachelor's in EE/ME/Materials or equivalent, 10+ years in package design or package-level simulation, strong package SI modeling and analysis experience, ability to build models and derive architecture guidance.
3mo
Save
Mark Applied
Hide
Package Architect – Advanced Packaging & System Exploration
Boise or San Jose
$177k-$387k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
10+ YOEBachelor’s degree or equivalent practical experience; 10+ years in package design or package-level simulation; strong SI modeling/analysis; ability to build models and drive conclusions.
SI modeling, Thermal simulation, Package design, Modeling tools
1mo
Save
Mark Applied
Hide
ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yr RemoteFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, SPICE, Vector Network Analysis, IBIS
3w
Save
Mark Applied
Hide
Staff Software Engineer, Pricing and Packaging Engineering
San Francisco or Denver or New York City or San Jose
$197k-$247k/yr HybridFull Time
Gusto
Gusto: Cloud-based payroll and HR software for small businesses.
8+ YOE8+ years building large-scale backend platform systems (commerce/billing/subscriptions preferred); strong distributed systems, API design, SLO, and mentorship experience; proven delivery of multi-quarter projects.
3w
Save
Mark Applied
Hide
Senior Package Design Engineer
San Jose or Taipei
$111k-$206k/yr HybridFull Time
Rambus
RambusNASDAQ: RMBS: Develops high-performance memory interface chips and semiconductor IP.
5+ YOEMS in EE/CE, 5+ years packaging design/layout experience, proficiency with Cadence Allegro Package Designer (APD) and AutoCAD, experience with multiple package types and high-speed routing, knowledge of substrate technologies and JEDEC standards.
Cadence Allegro Package Designer (APD), AutoCAD
1w
Save
Mark Applied
Hide
ASIC Package Design Manager
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
12+ YOE3+ MgmtManage and develop engineers for flip-chip-BGA package designs; requires 12+ years package design experience, 3+ years management, Ohio? (not stated), knowledge of SI/PI, project management and cross-functional collaboration.
1mo
Save
Mark Applied
Hide
Principal Package Design Engineer
San Jose, California, United States
$200k-$250k/yr HybridFull Time
Renesas Electronics
Renesas ElectronicsTokyo Stock Exchange: 6723: Designs and manufactures semiconductors for automotive and industrial systems.
5+ YOEMSc or PhD in engineering, 5+ years in semiconductor/advanced packaging, expertise in package architectures, reliability testing, thermal/mechanical/electrical interactions, OSAT collaboration, simulations, and NPI to production.
Cadence Allegro Package Designer, SolidWorks, ANSYS, COMSOL, JMP, Minitab
2mo
Save
Mark Applied
Hide
Senior Technical Program Manager (Silicon)
San Jose, California, United States
OnsiteFull Time
Lumilens
Lumilens: Designs photonic interconnects for AI supercomputing infrastructure.
10+ YOE10+ years in silicon design/tapeout, packaging, bring-up, validation; BS in EE/CE; strong PM skills.
MS Project, Jira, Asana, Smartsheet
2mo
Save
Mark Applied
Hide
PMIC Architect
San Jose or United States
$175k-$350k/yr HybridFull Time
TylSemi
TylSemi: Building chiplet-native infrastructure for high-performance AI systems.
15+ YOE5+ Mgmt15+ years in power IC architecture with principal-level experience; deep expertise in multi-phase buck converter design, mixed-signal IC design, integrated passive components, packaging, tape-out execution, and SPICE-level simulation.
SPICE, PMBus, I2C
1w
Save
Mark Applied
Hide
Signal and Power Integrity Senior Application Engineer
San Jose, California, United States
$84k-$156k/yr OnsiteFull Time
Cadence Design Systems
Cadence Design SystemsNASDAQ: CDNS: Develops computational software and hardware for electronic system design.
1+ YOEBachelor's or Master's in Electrical/Electronics Engineering, 1+ years related experience, strong background in signal, power, and electromagnetics for package and PCB design, excellent communication and presentation skills.
Sigrity, Clarity, PCB Editor, ICP, Cadence Allegro
2mo
Save
Mark Applied
Hide
Control Systems Services Manager
Walnut Creek or Modesto
$120k-$150k/yr OnsiteFull Time
E Tech Group
E Tech Group: Provides industrial automation and control systems integration services.
5+ YOE5+ years troubleshooting automated control systems (PLC & HMI); Rockwell PLC/HMI/SCADA experience; Ignition SCADA; electrical design packages; strong communication; field service leadership.
Rockwell PLC, Rockwell HMI, Ignition SCADA, Ethernet, ControlNet, DeviceNet, P&ID, Electrical drawings
2mo
Save
Mark Applied
Hide
Signal Integrity & Power Integrity Principal Engineer
San Jose, California, United States
$187k-$270k/yr OnsiteFull Time
Altera
Altera: Manufacturer of field-programmable gate arrays and programmable logic devices.
15+ YOE15+ years SI/PI experience; Bachelor's in Electrical/Computer Engineering; expertise in SI/PI for silicon/package/board; strong with HFSS/HSPICE/Sigrity/ADS; scripting in Python/MATLAB; design tool experience
ANSYS HFSS, Synopsys HSPICE, Cadence Sigrity, Keysight ADS, Mentor Graphics, Cadence Allegro, Python, MATLAB
1mo
Save
Mark Applied
Hide
Mechanical Design Engineer
Morgan Hill or Melbourne or Lowell or North America or Europe or Asia
$82k-$131k/yr OnsiteFull Time
MACOM
MACOMNASDAQ: MTSI: Designs and manufactures semiconductor products for communications infrastructure.
5+ YOEMechanical engineering degree with 5+ years in electronics packaging/assembly, proficiency in SolidWorks/AutoCAD and thermal analysis (Icepak preferred), GD&T, machining, tolerance/material selection, vendor coordination, BOM and DFM experience.
SolidWorks, Icepak, AutoCAD, PCB layout viewers, GD&T