17 physical synthesis implementation engineer jobs at 9 companies in United States
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Physical Synthesis Implementation Engineer
San Diego, California, United States
$99k-$148k/yr OnsiteFull Time
0+ YOEBachelor's degree in science/engineering, familiarity with Synopsys Design Compiler or Cadence Genus, scripting (TCL, Perl, Python), static timing analysis and VLSI concepts, strong communication; 0–1+ years hardware engineering experience.
Synopsys Design Compiler, Cadence Genus, TCL, Perl, Python
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Physical Design Engineer, Synthesis and Implementation
Westford, Massachusetts, United States
$116k-$219k/yr OnsiteFull Time
2+ YOEBSEE/MSEE or equivalent experience, 2+ years in synthesis and physical implementation, proficiency with synthesis tools, timing/QoR optimization, and scripting languages.
Synopsys Fusion Compiler, Cadence Genus, Python, Perl, Tcl, Make
3w
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Physical Design Engineer, Synthesis and Implementation
Westford, Massachusetts, United States
$116k-$219k/yr OnsiteFull Time
2+ YOEBSEE, MSEE, or equivalent experience; 2+ years in synthesis and physical implementation on advanced process nodes; synthesis, timing, QoR, place-and-route, debugging, and collaboration skills.
Synopsys Fusion Compiler, Cadence Genus, Python, Perl, Tcl, Make
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Physical Design Engineer, Synthesis and Implementation
Westford, Massachusetts, United States
$116k-$219k/yr OnsiteFull Time
2+ YOEBachelor's or master's degree in electrical engineering or equivalent experience; 2+ years in synthesis and physical implementation; expertise in timing, QoR, place-and-route, Python, Perl, Tcl, and Make.
Synopsys Fusion Compiler, Cadence Genus, Python, Perl, Tcl, Make
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CPU Gate Level Synthesis Engineer
Santa Clara or California
OnsiteFull Time
Bachelor's degree required; experience in digital logic design, RTL synthesis, or physical design. CPU implementation experience preferred; scripting and automation proficiency required.
TCL, Perl, Python, RTL, DFT, ATPG, MBIST
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Digital Physical Implementation and Integration Engineer
San Jose, California, United States
$145k-$246k/yr OnsiteFull Time
5+ YOERequires 5+ years of digital physical design, one full tapeout, and a bachelor's in computer or electrical engineering. Expertise with STA, APR, physical verification, synthesis, Tcl, Python or Perl, Linux, Git, and EDA tools.
PrimeTime, Cadence Innovus, Synopsys ICC2, Design Compiler, Genus, Calibre, Tcl, Python, Perl, Linux, Unix, Git, Make, Cadence Cerebrus, JedAI, Synopsys DSO.ai, MCP
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Senior Implementation Engineer, Amazon Leo
Sunnyvale or San Diego or Los Angeles County
$159k-$248k/yr OnsiteFull Time
7+ YOEBachelor's degree in Electrical Engineering or related field and 7+ years of ASIC implementation experience, including synthesis, STA, P&R, physical synthesis methodology, chip tape-outs, and multi-power-island designs.
UPF, RTL, Static Timing Analysis (STA), Logic Equivalence Checking (LEC), AI, P&R, DFT, RFIC, IR/EM
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Sr. Engineer, RTL Implementation
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experienced in high-performance physical design; RTL coding (Verilog/VHDL); synthesis/place-and-run; CPU micro-architecture.
Verilog, VHDL, Synthesis tools, Place and Route tools
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Implementation Methodology Engineer - GPU
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
4+ YOEBS/MS in EE/CE or equivalent; 4+ years in logic or physical design implementation; deep knowledge of synthesis, place-and-route, timing/power/area trade-offs; EDA tool expertise; Python/Tcl/Make scripting.
Synopsys DC, Synopsys FC, Cadence Genus, Cadence Innovus, EDA, Python, Tcl, Make
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GPU Design Implementation Engineer
San Diego, California, United States
$195k-$293k/yr OnsiteFull Time
4+ YOERequires a relevant bachelor's degree with 6+ years, master's with 5+ years, or PhD with 4+ years; expertise in ASIC implementation, synthesis, physical design, signoff tools, sub-micron tape-outs, and scripting.
Synopsys Next Generation tools, Conformal LEC, Synopsys Formality, Synopsys PrimeTime, Tcl, Perl, Python
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Implementation Methodology Engineer - GPU
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
4+ YOEBS or MS in Electrical/Computer Engineering; 4+ years in logic/physical design; strong optimization skills; experience with Synthesis and place-and-route tools (Synopsys DC/FC, Cadence Genus/Innovus); scripting in Python, Tcl, Make; strong collaboration and problem-solving.
Synopsys DC, Synopsys FC, Cadence Genus, Cadence Innovus, Python, Tcl, Make
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Physical Design Engineer - Block Level, Subsystem Implementation
San Jose, California, United States
OnsiteFull Time
5+ YOE5+ years physical design experience from RTL synthesis to GDSII sign-off, back-end timing closure on advanced nodes, EDA tool and scripting proficiency, and subsystem PPA optimization.
Cadence (Innovus), Cadence (Genus), Synopsys (Fusion Compiler), PrimeTime, Tempus, Voltus, GDSII, RTL, Unified Power Format (UPF), Tcl, Python, Perl
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Physical Design Engineer
San Jose, California, United States
$133k-$193k/yr OnsiteFull Time
5+ YOEBachelor's degree in a technical discipline and 5+ years of semiconductor physical design experience, including RTL-to-GDSII implementation, physical design flows, timing closure, and verification signoff.
RTL, GDSII, synthesis, floorplanning, place and route, clock tree synthesis (CTS), static timing analysis (STA), formal equivalence checking (LEC), IR drop, electromigration (EM), layout verification, electrical rule checking (ERC), design rule checking (DRC), layout versus schematic (LVS), Tcl, Python, Perl, Shell, UPF, CPF
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CPU Physical Design Engineer
Austin or Mountain View
$138k-$197k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent practical experience, 4 years of digital physical design implementation, and experience with synthesis, place and route, timing closure, and signoff tools.
Tcl, Python, Static Timing Analysis (STA), Place and Route (PnR), EMIR
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Sr. Physical Design Engineer, Amazon Leo
San Diego, California, United States
$159k-$215k/yr OnsiteFull Time
7+ YOEBachelor's degree in computer science, computer engineering, or electrical engineering and 7+ years of ASIC implementation experience, including synthesis, STA, DFT, and P&R.
RTL, STA, DFT, P&R, AI, ML, UPF
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Staff CPU Physical Design Engineer
Austin or Mountain View
$192k-$278k/yr OnsiteFull Time
10+ YOEBachelor's degree or equivalent practical experience and 10 years in high-performance, low-power physical design implementation or design convergence using synthesis, PnR, and signoff tools.
AI/ML
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Sr. Physical Design Engineer, Amazon Leo
Austin, Texas, United States
$159k-$215k/yr OnsiteFull Time
7+ YOEBachelor's degree in electrical engineering or related field and 7+ years of ASIC implementation experience, including synthesis, STA, DFT, and place-and-route for deep sub-micron nodes.
RTL, STA, DFT, P&R, UPF, ML, AI
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