6 post silicon validation engineer jobs at 4 companies in Los Angeles, CA
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Hardware and Silicon Validation
Westlake Village, California, United States
$109k-$162k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE/SE with 3–5 years (or Master's with 2–3 years). Experience in post‑silicon validation, RF/microwave/optical interconnects, proficiency in C/C++/Python, and hands‑on use of high‑speed test and measurement equipment.
C, C++, Python, Power supply, Multimeter, Spectrum analyzer, Oscilloscope, Bit error rate tester, Vector network analyzer (VNA), Arbitrary waveform generator (AWG), Lightwave components analyzer (LCA)
2mo
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Sr. ASIC DFT Engineer (Silicon)
Sunnyvale or Austin or Irvine
$135k-$185k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical or computer engineering or physics; 5+ years in DFT/post-silicon validation; strong scripting and test automation.
Perl, Python, Tcl, C++, Siemens Tessent
2w
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Principal Design Validation & Test (DVT) Engineer
Irvine, California, United States
OnsiteFull Time
8+ YOE8+ years post-silicon validation/DVT experience with complex ASICs/SoCs; Bachelor's in EE/CE/CS or related; Python skills; lab equipment and high-speed protocol expertise; strong debug and communication skills.
JTAG, Python, oscilloscopes, BERTs, protocol analyzers, network analyzers, logic analyzers, Ethernet traffic generators, power measurement equipment, PCIe, Ethernet, SerDes, CXL, SPI, I²C, MDIO, RTL
2mo
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Sr. ASIC DFT Engineer (Silicon)
Austin or Irvine or Sunnyvale
OnsiteFull Time
5+ YOEBachelor's in EE/CE/Physics; 5+ years in DFT and post-silicon validation; Masters/PhD preferred.
Siemens Tessent, ATPG, Design for Test (DFT), IEEE 1149.1, Teradyne, Advantest, Python, Perl, Tcl, C++
2w
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Principal DFT Engineer (Silicon Engineering)
Irvine or Austin or Palo Alto
$210k-$340k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE/CS,10+ years ASIC and DFT experience including scan insertion, ATPG, and post-silicon validation; strong RTL, debugging, and scripting skills.
Siemens Tessent, Perl, Python, Tcl, C+, Verilog, SystemVerilog, UPF, SDF, DRC, ATE
2mo
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Analog ATE Test Engineer
Aliso Viejo, California, United States
OnsiteFull Time
5+ YOE5–8+ years analog ATE test engineering experience (8+ with BS EE or 5+ with MS), production experience with Advantest V93000 and SmarTest 8, Python and Java programming, post-silicon validation and PCB debugging experience.
Advantest V93000, SmarTest 8, Python, Java