5 principal engineer software development jobs at 1 company in Temple, TX
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Senior Principal Systems Development Engineer
Round Rock or Santa Clara
$183k-$237k/yr OnsiteFull Time
13+ YOERequires 13+ years of software development experience in networking switch diagnostics, ONIE, BMC, BIOS, firmware, UEFI, EDKII, Broadcom SDK, and PHY drivers; cross-functional leadership ability.
ONIE, BMC, BIOS, PFR, RoT, eROT, Security Development Lifecycle (SDL), UEFI, EDKII, Broadcom SDK, PHY drivers
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Principal Systems Development Engineer
Round Rock, Texas, United States
$148k-$204k/yr OnsiteFull Time
8+ YOERequires 8+ years of related experience with a bachelor's degree or 6+ years with a master's degree, server architecture expertise, PCIe, storage and network protocols, and hardware-software interaction knowledge.
PCIe, Python, C, C++, Linux, shell scripting
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Principal Systems Development Engineer
Round Rock or Hopkinton or Santa Clara
$157k-$204k/yr OnsiteFull Time
8+ YOE8+ years professional experience with Bachelor's (or 6+ with Master\u0002s/3+ with PhD) or equivalent; system-level rack-scale architecture, integration across compute/mechanical/thermal/software/diagnostics, testing, root-cause analysis, and cross-team collaboration.
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Senior Principal Software Engineer - (Modernization, Automation & AI)
Round Rock, Texas, United States
$147k-$202k/yr OnsiteFull Time
12+ YOE12+ years enterprise software engineering with 7+ years ServiceNow development; expertise in App Engine, Flow Designer, IntegrationHub, ServiceNow Studio, UI Builder, Workspaces, JavaScript, REST integrations, MID Server, and AI-assisted development.
App Engine, Flow Designer, IntegrationHub, ServiceNow Studio, UI Builder, Workspace, Service Catalog, JavaScript, REST APIs, MID Server, Import Sets, Now Assist, Build Agent, CI/CD, Git, ATF
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Senior Principal Electrical Engineer - FPGA Development
Round Rock, Texas, United States
$174k-$226k/yr OnsiteFull Time
12+ YOE12+ years product development experience; advanced FPGA technologies, Verilog/SystemVerilog and HDL coding; RTL design and simulation; strong analog and digital fundamentals; hardware-software integration. Toolchain experience (Lattice/Xilinx/Altera, Synopsys VCS), Python and Git preferred.
Verilog, SystemVerilog, HDL, RTL, Lattice, Xilinx, Altera, Synopsys VCS, Python, Batch, Git