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6 principal quality engineer jobs at 4 companies in Pacific Grove, CA

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Principal Quality Engineer
Campbell, California, United States
$173k-$192k/yr OnsiteFull Time
Imperative Care
Imperative Care: Develops medical devices for stroke and vascular disease treatment.
12+ YOEBS in Engineering and 12+ years relevant experience (or equivalent); expertise in sterilization, microbiology and biocompatibility; strong knowledge of ISO standards and FDA 21 CFR Part 820; risk management, CAPA and audit experience; Microsoft Office proficiency.
Microsoft Office
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1mo
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Principal Supplier Quality Engineer
San Jose, California, United States
$152k-$218k/yr OnsiteFull Time
Bloom Energy
Bloom EnergyNYSE: BE: Manufactures solid oxide fuel cell systems for onsite power.
10+ YOE10+ years quality experience with supplier quality, QMS auditing, SPC, DFMEA/PFMEA, 8D, DOE/ANOVA, project management, and cross-functional leadership in manufacturing environments.
Microsoft Word, Microsoft Excel, Microsoft PowerPoint, JMP, R, Tableau
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1mo
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Sr. Principal Technical Quality Engineer
San Jose or Austin or Cary
$154k-$286k/yr OnsiteFull Time
Cadence Design Systems
Cadence Design SystemsNASDAQ: CDNS: Develops computational software and hardware for electronic system design.
7+ YOEMSEE and 7+ years experience in IC design/verification or silicon quality; defect analysis and RCA experience; strong communication and problem-solving skills.
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3mo
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Principal Process Development Engineer
Campbell, California, United States
$182k-$192k/yr OnsiteFull Time
Imperative Care
Imperative Care: Develops medical devices for stroke and vascular disease treatment.
12+ YOESenior engineer with 12+ years in medical device process development; DOE/validation; FDA/quality systems; strong analytics and project leadership.
Excel, Minitab, JMP, DOEs, DMAIC, FDA Design Control
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2d
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Principal RTL Design Engineer
San Jose, California, United States
$180k-$255k/yr OnsiteFull Time
SambaNova Systems
SambaNova Systems: Develops custom AI hardware and software for enterprise computing.
7+ YOERequires BS or MS in EE, CE, or CS and 7+ years of ASIC RTL design experience, with SystemVerilog, high-frequency design, physical design, timing analysis, quality flows, Python, and technical leadership.
SystemVerilog, SystemVerilog Assertions, Python, SVA, AXI, PCIe, Ethernet, HBM, DDR, Claude
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14h
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Principal RTL Design Engineer
Austin or San Jose
$180k-$255k/yr OnsiteFull Time
SambaNova Systems
SambaNova Systems: Develops custom AI hardware and software for enterprise computing.
7+ YOEB.S. required; 7+ years of ASIC RTL experience, advanced SystemVerilog, high-frequency design, computer architecture, production ASIC tape-out, physical design constraints, quality flows, technical leadership, and Python scripting.
SystemVerilog, SystemVerilog Assertions (SVA), Python, AXI, PCIe, Ethernet, HBM, DDR, TSMC, Claude
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