10 python script developer jobs at 4 companies in Gridley, CA
2d
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Principal Engineer - Design
Roseville, California, United States
$75k-$232k/yr OnsiteFull Time
10+ YOE10+ years experience in SoC design/verification, BS/MS in Electrical/Computer Engineering, experience with serial protocols (SAS/SATA/NVMe, PCIe), Linux and C/Python scripting, RTL (VHDL/Verilog/System Verilog).
Cadence Palladium, Protium, Linux, C, Python, Tcl, Bash, VHDL, Verilog, System Verilog, JTAG, I2C
3mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOEBachelor's or Master's in Electrical/Computer Engineering; 6-10 years VLSI design/verification; Verilog/SystemVerilog/UVM; scripting (Python/Perl/TCL); C/C++; EDA/verification tools.
Verilog, SystemVerilog, UVM, Specman, Python, Perl, TCL, C, C++, EDA tools
3mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOE6-10 years in VLSI design/verification; BS/MS in Electrical or Computer Engineering; scripting (Python/Perl/TCL); programming (C/C++); Verilog/SystemVerilog; UVM; knowledge of EDA tools.
Verilog, SystemVerilog, UVM, Python, Perl, TCL, C, C++
3mo
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ASIC Senior Verification Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOESenior verification engineer with 10+ years in VLSI design/verification; strong Verilog/SystemVerilog, UVM; scripting (Python, Perl, TCL); C/C++; leadership.
Verilog, SystemVerilog, UVM, Python, PERL, TCL, C, C++, Specman
3mo
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ASIC Senior Verification Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOE10+ years in VLSI design/verification; FPGA/EDA; Verilog/SystemVerilog; scripting (Python, TCL, PERL); C/C++; UVM; BS or MS in EE/CS.
Verilog, SystemVerilog, UVM, EDA, C, C++, Python, Perl, TCL
2d
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Principal Engineer - Validation (Systems)
Roseville, California, United States
$75k-$232k/yr OnsiteFull Time
10+ YOE10+ years SoC/silicon validation experience, strong C/C++ and Python scripting, hands-on lab skills with high-speed test equipment, SoC system-level debug, and a BS/MS in Computer/Electrical Engineering or Computer Science.
C, C++, Python, Tcl, oscilloscope, protocol analyzer, logic analyzer, FPGA, VHDL, Verilog, Linux, Windows, PCIe, DDR4, DDR5, SAS, SATA, I2C, SPI, ThreadX, RTOS, MIPS
2mo
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Senior ASIC verification engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOEBachelor's degree in EE/CE, 10+ years VLSI design/verification experience, proficiency in Verilog/SystemVerilog, UVM, scripting (Python, Perl, Tcl), C/C++, strong VLSI architecture and leadership skills.
Python, Perl, Tcl, C, C++, Verilog, SystemVerilog, UVM, Specman, Electronic Design Automation (EDA), FPGA tools
1mo
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Controls & Instrumentation Engineer
Roseville, California, United States
$85k-$100k/yr OnsiteFull Time
Bachelor's in Mechanical, Electrical, or Controls Engineering (or equivalent experience); PLC and SCADA experience (Ignition preferred); IEC 61131-3 languages (Structured Text, Ladder Logic); Modbus TCP, OPC UA, Ethernet/IP; OT network knowledge; Python/Jython scripting.
Ignition, Enterprise Administration Module (EAM), Python, Jython, Schneider Electric M251, Schneider Electric M580, EcoStruxure Machine Expert, IEC 61131-3, Structured Text, Ladder Logic, Modbus TCP, OPC UA, Ethernet/IP, VLAN
2mo
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Infrastructure Automation Engineer 2
Folsom or Denver or Englewood or Minneapolis or St. Paul or Pennington or Woodcliff Lake or Olympia
OnsiteFull Time, Full Time
3+ YOE3+ years in infrastructure automation, DevOps or related roles; strong scripting (Python/PowerShell/JavaScript), REST APIs, CI/CD, Git; Terraform/Ansible knowledge; IT service management understanding; Bachelor’s degree or equivalent.
Python, PowerShell, JavaScript, REST APIs, Git, CI/CD, Terraform, Ansible
3mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOE Bachelor's or Master in Electrical or Computer Engineering; 6-10 years in VLSI design/verification; scripting and programming experience; strong VLSI knowledge.
Python, Perl, TCL, C, C++, Verilog, SystemVerilog, UVM, Specman