16 python script developer jobs at 6 companies in Monterey, CA
2mo
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Embedded Software Engineer II , Connectivity Systems at eero
Los Gatos, California, United States
$165k-$224k/yr OnsiteFull Time
3+ YOE3+ years software development; embedded Linux experience; C/C++ and scripting (Python or Go); Bachelor's in related field.
C/C++, Python, Golang, Linux, Yocto/BitBake
4w
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
1w
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SoC Design Verification Engineer
San Jose, California, United States
$124k-$213k/yr HybridFull Time
Experience in SoC/CPU verification, testbench development, and verification metrics; strong coding in Verilog/System Verilog, UVM, C/C++, scripting (Perl/Python); Bachelors/Masters in computer or electrical engineering.
Verilog, System Verilog, UVM, C, C++, Perl, Python
5d
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DevOps Engineer
Monterey, California, United States
$95k-$105k/yr OnsiteFull Time
3+ YOE3+ years network/DevOps experience, AA/AS or equivalent, IAT Level II and Public Trust, proficiency with Linux/Windows, VMware ESXi, scripting (Python/Bash/Ruby), Docker and orchestration, CI/CD and cloud platforms.
VMware ESXi, Python, Bash, Ruby, Docker, ECS, Kubernetes, GitLab, Microsoft Team Foundation, SAN, Azure, GCP
1mo
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Senior Embedded Software Engineer - Flight Software
Saratoga, California, United States
$130k-$180k/yr OnsiteFull Time
Design and develop real-time embedded/flight software for bare-metal, RTOS, and real-time Linux; strong C/C++ and scripting (Shell/Bash/Python); experience with networking, space communication protocols, debugging tools, and embedded test frameworks.
C/C++, Shell, Bash, Python, Yocto, JTAG, GDB, Git, UART, CAN, SpaceWire, SPI, I2C, Ethernet, real-time Linux, RTOS, TSN, TTC (CCSDS protocol), Distributed Switch Architecture (DSA), RSTP, MSTP, HSR, FRER, HIL, SIL, PIL, oscilloscope, logic analyzer, protocol analyzer, serial debugger
1mo
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RTL Design Engineer
San Jose, California, United States
HybridFull Time
Experience in RTL digital design and verification, Verilog/System Verilog, scripting (Perl/Tcl/Python), FPGA/SoC design concepts, and strong analytical and communication skills; Bachelor’s or Master’s in Computer or Electrical Engineering.
Verilog, System Verilog, Perl, Tcl, Python
1mo
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Principal PIC Characterization Engineer
Los Gatos, California, United States
OnsiteFull Time
5+ YOE5+ years industry experience in silicon photonics or optical communications; hands-on wafer-scale probe and PIC characterization; Python/MATLAB scripting; high-speed optical measurement experience.
Python, MATLAB, JMP, VNA, DAC, ADC
1w
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Silicon Design Engineer
San Jose, California, United States
$146k-$250k/yr OnsiteFull Time
Experience owning RTL-to-GDS physical implementation, place-and-route, timing closure, physical verification, PrimeTime/STA, Cadence Innovus/Genus or Synopsys Fusion, scripting (Tcl, Python, shell); advanced degree preferred; must be eligible to work without visa sponsorship.
Design Compiler, PrimeTime, Cadence Innovus, Genus, Synopsys Fusion Compiler, EMIR, Tcl, Python, shell
3mo
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Senior EM/IR Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOE8+ years EM/IR analysis for complex ASICs/SoCs; power integrity; PDN design and sign-off; Verilog/SystemVerilog/UVM; scripting (Python/Tcl); experience with Cadence Voltus and Synopsys RedHawk.
Cadence Voltus, Synopsys RedHawk, Verilog, SystemVerilog, UVM, VHDL, Tcl, Python
1mo
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SoC Physical Integration Engineer
San Jose, California, United States
$104k-$178k/yr HybridFull Time
Bachelor's degree in EE (Master's preferred); experience in SoC physical/electrical verification and tape-out; familiarity with physical implementation and P&R tools; simulation with SPICE/Verilog; scripting (Perl, Python, TCL, C-shell, Make); Unix/Linux.
Virtuoso, ICC2, FC, Innovus, SPICE, Verilog, RTL, Place and Route (P&R), Perl, Python, TCL, C-shell, Make, Unix/Linux, CAD
1w
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Thermal Engineer
San Jose, California, United States
$146k-$250k/yr OnsiteFull Time
Experience in thermal analysis, modeling, characterization, and validation of electronic systems; proficiency with CFD/thermal simulation tools and scripting for data analysis; strong heat transfer fundamentals; Master's or PhD in relevant engineering.
Ansys Icepak, AEDT, FloTHERM, FloTHERM XT, Python, MATLAB, SolidWorks, Creo, Linux, Windows
1mo
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RTL / Circuit IP Design Engineer
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Design and implement RTL/IP features; strong RTL/Verilog/System Verilog, UVM, UPF, SAPR, and simulation/debugging skills; scripting (Python/Perl/Ruby/Makefile/shell); Bachelors or Masters in computer/electrical engineering required.
RTL, UVM, Linux, Windows, Verilog, System Verilog, Python, Perl, Ruby, Makefile, shell, HLS, SAPR, UPF
2w
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Senior Applications Engineer
Scotts Valley, California, United States
$130k-$160k/yr OnsiteFull Time
5+ YOE5+ years in power electronics or related hardware environments; strong DC circuit fundamentals; scripting and test-automation skills; familiarity with power conversion, BMS, protection, thermal loops, lab instrumentation, and comms protocols.
Python, CAN, Modbus TCP, LTspice, Simscape, PLECS, DAS, SCADA, EMS, BMS, oscilloscopes, power analyzers, DAQ systems
2mo
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MTS Product Application Eng.
San Jose, California, United States
$141k-$241k/yr OnsiteFull Time
In-depth system-level understanding of embedded and x86-based processing systems; strong expertise in x86 architecture; knowledge of compilers, operating systems, debuggers, and hardware interfaces; proficient in Python, C/C++, and scripting.
Linux, BIOS, UEFI, Bootloaders, Python, Perl, C/C++, Assembly, DDR4/DDR5, PCIe Gen3/Gen4/Gen5, Ethernet
2w
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Design Verification Lead
San Jose, California, United States
$200k-$300k/yr HybridFull Time
10+ YOEMinimum 10 years UVM design verification experience; Bachelor's or Master's in EE/CE/CS or related; expertise in SystemVerilog/Verilog, UVM, high-speed protocol verification (PCIe, CXL, Ethernet); scripting with Python/Perl; technical leadership and mentoring.
UVM, SystemVerilog, Verilog, PCIe, CXL, Ethernet, Python, Perl, HLS
2mo
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DFx Methodology Architect
San Jose, California, United States
OnsiteFull Time
Bachelor or Master in computer engineering or Electrical Engineering; experience with RTL design, DFx, IP development, and scripting languages.
Perl, TCL, Python, Verilog