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Design Engineering Intern
San Jose, California, United States
$35-$45/hr OnsiteInternship, Full Time
Proficiency in Verilog/SystemVerilog, RTL coding, Synopsys VCS simulation and debugging; BS/MS in EE/ECE/CS completed or in progress; able to work 40 hours/week onsite for 6 months.
Verilog, SystemVerilog, Synopsys VCS, Python, Perl, Tcl
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Digital Physical Design (P&R) Intern
Chandler, Arizona, United States
OnsiteFull Time
Pursuing MSEE with digital design coursework, knowledge of digital backend flow from synthesis to GDS2, willing to relocate to Phoenix metro and work minimum 3 days/week onsite; strong problem-solving and teamwork skills; prior flow experience a plus.
Cadence, GDS2, RTL, Synthesis