1w
Save
Mark Applied
Hide
Senior Customer Quality Engineer
San Jose, California, United States
$149k-$256k/yr OnsiteFull Time
Experienced quality engineer with semiconductor or related industry background; skilled in customer engagements, root-cause analysis, structured quality methods (8D, RCA, FMEA, Six Sigma); BS in engineering preferred.
8D, RCA, FMEA, Six Sigma, x86 processors, GPUs, FPGAs
1mo
Save
Mark Applied
Hide
Sr. Thermal & Mechanical Packaging Engineer, Annapurna Labs
Tempe or Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
10+ YOEMaster's in mechanical engineering; 5+ years in advanced semiconductor packaging and 10+ years in mechanical design of semiconductor systems; experience with vendors/ODMs; proficiency with ANSYS, ABAQUS, COMSOL, FLOTHERM, ICEPACK.
ANSYS, ABAQUS, COMSOL, FLOTHERM, ICEPACK
4d
Save
Mark Applied
Hide
CQE – Customer Quality Engineer
San Jose, California, United States
$160k-$240k/yr OnsiteFull Time
Technical customer-quality experience in semiconductor or related industries, structured problem-solving (8D/RCA/FMEA), strong communication, bachelor's in engineering required; master's preferred.
8D, Root Cause Analysis (RCA), Failure Mode and Effects Analysis (FMEA), Six Sigma
3w
Save
Mark Applied
Hide
Quality Engineer - Assembly
Morgan Hill, California, United States
$59k-$97k/yr OnsiteFull Time
5+ YOEBachelor's in engineering, minimum 5 years' semiconductor/manufacturing quality experience, knowledge of AS9100D/ISO9001, MIL-STD-883, IPC-A-610, 8D/FMEA/SPC/MSA, SQL/JMP/Microsoft Office proficiency, U.S. Person (ITAR) required.
SQL, JMP, Microsoft Office 365
1mo
Save
Mark Applied
Hide
Senior/Staff Power Electronics Engineer
Scotts Valley, California, United States
$120k-$200k/yr OnsiteFull Time
3+ YOEDegree in electrical engineering or equivalent experience, minimum 3 years hands-on power converter design/prototyping/industrialization, proficiency with power semiconductor devices, magnetic design, PCB layout, simulation tools and lab instrumentation; US work authorization required.
SPICE, PLECS, LTspice, Simulink, Python, LabVIEW, oscilloscopes, network analyzers, power analyzers
2mo
Save
Mark Applied
Hide
Principal DV Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
10+ YOE10+ years of design verification experience in semiconductors; expert Verilog/SystemVerilog/UVM; C/C++ and Python; leadership experience; ability to verify ASICs and lead verification efforts.
Verilog, SystemVerilog, UVM, VHDL, C++, Python, Perl, Bash
3w
Save
Mark Applied
Hide
Sr. Staff PIC Platform Engineer
Los Gatos, California, United States
OnsiteFull Time
5+ YOE5+ years in semiconductor process or foundry interface roles; experience with silicon photonics/CMOS; expertise in wafer fabrication, yield analysis, SPC/DOE, root-cause methods; strong cross-functional communication.
JMP, Python, MATLAB
1mo
Save
Mark Applied
Hide
Velocity Automation/Applications (EDA to ATE Conversion)
San Jose, California, United States
OnsiteFull Time
Bachelor’s or Master’s in Electrical Engineering, Computer Science, or related field; experience with semiconductor EDA-to-ATE conversion; hands-on with Velocity, Test Insight, VTRAN, or TSSI; knowledge of DFT and test methodologies; experience with STIL/WGL/EVCD; programming in Python, Java, Perl, C++; strong debugging and communication skills.
Velocity, Test Insight, VTRAN, TSSI, STIL, WGL, EVCD, Python, Java, Perl, C++
1mo
Save
Mark Applied
Hide
Director Silicon Design Engineering
San Jose, California, United States
HybridFull Time
15+ YOE5+ Mgmt15+ years ASIC/semiconductor leadership; strong hands-on design and program management; FPGA experience a plus; deep ASIC development lifecycle knowledge.
RTL, ASIC, Analog Design, Digital Design, Tapeout, Post-Silicon Validation
2mo
Save
Mark Applied
Hide
Director, Product Development Engineering-ASIC/SoC
San Jose, California, United States
OnsiteFull Time
Semiconductor business development experience; ASIC/SoC/custom FPGA knowledge; leadership of large cross-functional teams; strong strategic, financial, and communication skills.
ASIC, SoC, FPGA, IP, packaging, software, financial modeling
2mo
Save
Mark Applied
Hide
Director, Product Development Engineering-ASIC/SoC
San Jose, California, United States
$204k-$349k/yr OnsiteFull Time
Experience in semiconductor business development and custom ASIC/SoC solutions; strong technical understanding of chip architecture, IP, packaging, and design ecosystems; proven ability to manage large customer engagements and executive relationships.
ASIC, SoC, FPGA, IP, packaging, design tools
3w
Save
Mark Applied
Hide
Integrated Circuit Packaging Architect
San Jose, California, United States
$183k-$314k/yr HybridFull Time
Proven track record in semiconductor technology development and leadership; define package architecture, DFM/DFY and yield roadmaps; collaborate with product architects and manufacturing partners; strong communication skills; BS/MS/PhD in related fields.
3w
Save
Mark Applied
Hide
Engineering Project Manager – Photonic Integrated Circuit (PIC) Fabrication
Sunnyvale or San Jose
$119k-$220k/yr OnsiteFull Time
2+ YOEBachelors or Masters in engineering/physics/optics/materials science; 2+ years in hardware engineering, product development, or project management; experience with Smartsheet and Jira; strong communication and semiconductor/cleanroom familiarity preferred.
Smartsheet, Jira
1mo
Save
Mark Applied
Hide
Senior CAD Manager — RTL-to-GDS Methodology & Infrastructure, Annapurna Labs
Cupertino, California, United States
$240k-$324k/yr OnsiteFull Time
15+ YOE5+ MgmtBachelor's in electrical or computer engineering; 15+ years in semiconductor CAD/EDA or physical design; 5+ years in leadership; experience with RTL-to-GDS toolchains; knowledge of low-power design and automation.
Tcl, Python, Perl, Git, Perforce, LSF, Slurm